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| 1 features ? high-performance and low-power avr ? 8-bit risc architecture ? 118 powerful instructions ? most single cycle execution ? 32 x 8 general purpose working registers ? up to 8 mips throughput at 8 mhz data and non-volatile program memory ? 4k bytes of in-system programmable flash endurance 1,000 write/erase cycles ? 128 bytes of sram ? 256 bytes of in-system programmable eeprom endurance: 100,000 write/erase cycles ? programming lock for flash pr ogram and eeprom data security peripheral features ? one 8-bit timer/counter with separate prescaler ? expanded 16-bit timer/counter with separate prescaler, compare, capture modes a nd 8-, 9-, or 10-bit pwm ? on-chip analog comparator ? programmable watchdog timer with separate on-chip oscillator ? programmable uart ? 6-channel, 10-bit adc ? master/slave spi serial interface special microcontroller features ? brown-out reset circuit ? enhanced power-on reset circuit ? low-power idle and power-down modes power consumption at 4 mhz, 3v, 25 c ? active: 3.4 ma ? idle mode: 1.4 ma ? power-down mode: <1 a i/o and packages ? 20 programmable i/o lines ? 28-lead pdip and 32-lead tqfp operating voltage ? 2.7v - 6.0v for the at90ls4433 ? 4.0v - 6.0v for the at90s4433 speed grades ? 0 - 4 mhz for the at90ls4433 ? 0 - 8 mhz for the at90s4433 8-bit microcontroller with 4k bytes of in-system programmable flash at90s4433 at90ls4433 not recommend for new designs. use atmega8. rev. 1042h?avr?04/03
2 at90s/ls4433 1042h?avr?04/03 pin configurations tqfp top view pdip 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (int1) pd3 (t0) pd4 nc vcc gnd nc xtal1 xtal2 pc1 (adc1) pc0 (adc0) nc agnd aref nc avcc pb5 (sck) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (t1) pd5 (ain0) pd6 (ain1) pd7 (icp) pb0 (oc1) pb1 (ss) pb2 (mosi) pb3 (miso) pb4 pd2 (int0) pd1 (txd) pd0 (rxd) reset pc5 (adc5) pc4 (adc4) pc3 (adc3) pc2 (adc2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 reset (rxd) pd0 (txd) pd1 (int0) pd2 (int1) pd3 (t0) pd4 vcc gnd xtal1 xtal2 (t1) pd5 (ain0) pd6 (ain1) pd7 (icp) pb0 pc5 (adc5) pc4 (adc4) pc3 (adc3) pc2 (adc2) pc1 (adc1) pc0 (adc0) agnd aref avcc pb5 (sck) pb4 (miso) pb3 (mosi) pb2 (ss) pb1 (oc1) 3 at90s/ls4433 1042h?avr?04/03 description the at90s4433 is a low-power cmos 8- bit microcontroller based on the avr risc architecture. by executing powerful instruct ions in a single clock cycle, the at90s4433 achieves throughputs approaching 1 mips per mhz, allowing the system designer to optimize power consumption versus processing speed. the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the at90s4433 provides the following featur es: 4k bytes of in-system programmable flash, 256 bytes of eeprom, 128 bytes of sram, 20 general purpose i/o lines, 32 general purpose working registers, two flexible timer/counters with compare modes, internal and external interrupts, a programmable serial uart, 6-channel, 10-bit adc, programmable watchdog timer with internal oscillator, an spi serial port and two soft- ware-selectable power-saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscill ator, disabling all other chip functions until the next interrupt or hardware reset. the device is manufactured using atmel?s high-density non-volatile memory technology. the on-chip flash program memory can be re-programmed in-system through an spi serial interface or by a conventional non-volatile memory programmer. by combining a risc 8-bit cpu with in-system programmabl e flash on a monolithic chip, the atmel at90s4433 is a powerful microcontroller that provides a highly flexible and cost-effec- tive solution to many embedded control applications. the at90s4433 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-cir- cuit emulators and evaluation kits. table 1. comparison table device flash eeprom sram voltage range frequency at90s4433 4k 256b 128b 4.0v - 6.0v 0 - 8 mhz at90ls4433 4k 256b 128b 2.7v - 6.0v 0 - 4 mhz 4 at90s/ls4433 1042h?avr?04/03 block diagram figure 1. the at90s4433 block diagram program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. portc data register portb data register portc analog mux adc data register portd programming logic timing and control oscillator interrupt unit eeprom spi uart status register z y x alu portb drivers portc drivers portd drivers pb0 - pb5 pc0 - pc5 reset vcc avcc agnd aref gnd xtal2 xtal1 control lines + - analog comparator pd0 - pd7 8-bit data bus data dir. reg. portd 5 at90s/ls4433 1042h?avr?04/03 pin descriptions vcc supply voltage. gnd ground. port b (pb5..pb0) port b is a 6-bit bi-directional i/o port with internal pull-up resistors. the port b output buffers can sink 20 ma. as i nputs, port b pins that are ex ternally pulled low will source current if the pull-up resistors are activated. port b also serves the functions of variou s special features of the at90s4433 as listed on page 73. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c (pc5..pc0) port c is a 6-bit bi-directional i/o port with internal pull-up resistors. the port c output buffers can sink 20 ma . as inputs, port c pins that ar e externally pulled low will source current if the pull-up resistors are activated. port c also serves as the analog inputs to the a/d converter. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors. the port d output buffers can sink 20 ma . as inputs, port d pins that ar e externally pulled low will source current if the pull-up resistors are activated. port d also serves the functions of various special features of the at90s4433 as listed on page 81. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. reset reset input. an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit xtal2 output from the invert ing oscillator amplifier avcc avcc is the supply voltage for port a and the a/d converter. if the adc is not used, this pin must be connected to v cc . if the adc is used, this pin should be connected to v cc via a low-pass filter. see page 64 for details on operation of the adc. aref aref is the analog reference input for the a/d converter. for adc operations, a volt- age in the range 2.0v to avcc must be applied to this pin. agnd if the board has a separate analog ground plane, this pin should be connected to this ground plane. otherwise, connect to gnd. 6 at90s/ls4433 1042h?avr?04/03 clock options crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier, which can be configured for use as an on-chip oscillator, as shown in figure 2 and figure 3. either a quartz crystal or a ceramic resonator may be used. external clock if the oscillator is to be used as a clock for an external device, the clock signal from xtal2 may be routed to one hc buffer while reducing the load capacitor by 5 pf, as shown in figure 3. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 4. figure 2. oscillator connections figure 3. using mcu oscillator as a clock for an external device figure 4. external clock drive configuration xtal1 reduce by 5 p f max 1 hc buffer xtal2 hc 7 at90s/ls4433 1042h?avr?04/03 architectural overview the fast-access register file concept contains 32 x 8-bit general purpose working reg- isters with a single clock cycle access time. this means that during one single clock cycle, one arithmetic logic unit (alu) operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing, enabling efficient address calculations. one of the three address pointers is also used as the address pointer for the constant table look-up func- tion. these added function registers are the 16-bit x-, y-, and z-register. the alu supports arithmetic and logic functions between registers or between a con- stant and a register. single register operations are also executed in the alu. figure 5 shows the at90s4433 avr risc microcontroller architecture. in addition to the register operation, the conventional memory addressing modes can be used on the register file as well. this is enabled by the fact that the register file is assigned the 32 lowermost data space addresses ($00 - $1f), allowing them to be accessed as though they were ordinary memory locations. figure 5. the at90s4433 avr risc architecture 2k x 16 program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control interrupt unit spi unit 8-bit timer/counter watchdog timer analog to digital converter analog comparator 20 i/o lines 256 x 8 eeprom data bus 8-bit serial uart 16-bit timer/counter with pwm 128 x 8 data sram direct addressing indirect addressing 8 at90s/ls4433 1042h?avr?04/03 the i/o memory space contains 64 addresses for cpu peripheral functions such as control registers, timer/counters, a/d converters and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, $20 - $5f. the avr uses a harvard architecture concept ? with separate memories and buses for program and data. the program memory is executed with a two-stage pipeline. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructi ons to be executed in every clock cycle. the program memory is in-system programmable flash memory. with the relative jump and call instructions, the whole 2k word address space is directly accessed. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram and, consequently, the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the 8-bit stack pointer (sp) is read/write accessible in the i/o space. the 128 bytes of data sram can be easily accessed through the five different address- ing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. 9 at90s/ls4433 1042h?avr?04/03 figure 6. at90s4433 memory maps a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all the different interrupts have a sep- arate interrupt vector in the interrupt vector table at the beginning of the program memory. the different interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. 32 gen. purpose working registers 64 i/o registers internal sram (128 x 8) $0000 $001f $005f $0060 $00df $0020 $000 $7ff data memory program memory program flash (2k x 16) 10 at90s/ls4433 1042h?avr?04/03 general purpose register file figure 7 shows the structure of the 32 general purpose working registers in the cpu. figure 7. avr cpu general purpose working registers all the register operating instructions in the instruction set have direct and single cycle access to all registers. the only exceptions are the five constant arithmetic and logic instructions sbci, subi, cpi, andi, and ori between a constant and a register, and the ldi instruction for load immediate constant data. these instructions apply to the second half of the registers in the register file (r16..r31). the general sbc, sub, cp, and, and or, and all other operations between two registers or on a single register apply to the entire register file. as shown in figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being phys- ically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x- , y- ,and z-registers can be set to index any register in the file. x-register, y-register and z- register the registers r26..r31 have some added f unctions to their general purpose usage. these registers are address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as: figure 8. x-, y-, and z-registers 7 0 addr. r0 $00 r1 $01 r2 $02 ? r13 $0d general r14 $0e purpose r15 $0f working r16 $10 registers r17 $11 ? r26 $1a x-register low byte r27 $1b x-register high byte r28 $1c y-register low byte r29 $1d y-register high byte r30 $1e z-register low byte r31 $1f z-register high byte 15 0 x - register 7 0 7 0 r27 ($1b) r26 ($1a) 15 0 y - register 7 0 7 0 r29 ($1d) r28 ($1c) 15 0 z - register 7 0 7 0 r31 ($1f) r30 ($1e) 11 at90s/ls4433 1042h?avr?04/03 in the different addressing modes, these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all the 32 general purpose working registers. within a single clock cycle, alu operations between regis- ters in the register file are executed. the alu operations are divided into three main categories: arithmetic, logical, and bit functions. in-system programmable flash program memory the at90s4433 contains 4k bytes of on-c hip, in-system programmable flash memory for program storage. since all instructions are 16- or 32-bit words, the flash is orga- nized as 2k x 16. the flash memory has an endurance of at least 1,000 write/erase cycles. the at90s4433 program counter (pc) is 11 bits wide, thus addressing the 2,048 program memory addresses. see page 93 for a detailed description of flash data downloading. see page 12 for the different program memory addressing modes. figure 9. sram organization sram data memory figure 9 shows how the at90s4433 sram memory is organized. the lower 224 data memory locations address the register file, the i/o memory and the internal data sram. the first 96 locations address the register file and i/o mem- ory, and the next 128 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with dis- placement, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. register file data address space r0 $0000 r1 $0001 r2 $0002 o o r29 $001d r30 $001e r31 $001f i/o registers $00 $0020 $01 $0021 $02 $0022 ?? $3d $005d $3e $005e $3f $005f internal sram $0060 $0061 o $00de $00df 12 at90s/ls4433 1042h?avr?04/03 the direct addressing reaches the entire data space. the indirect with displacement mode features 63 address locations reached from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers x, y, and z are decremented and incremented. the 32 general purpose working registers, 64 i/o registers and the 128 bytes of inter- nal data sram in the at90s4433 are all accessible through all these addressing modes. see the next section for a detailed description of the different addressing modes. program and data addressing modes the at90s4433 avr risc microcontroller supports powerful and efficient addressing modes for access to the flash program memory, sram, register file, and i/o data memory. this section describes the different addressing modes supported by the avr architecture. in the figures, op means the operation code part of the instruction word. to simplify, not all figures show the exact location of the addressing bits. register direct, single register rd figure 10. direct single register addressing the operand is contained in register d (rd). register direct, two registers rd and rr figure 11. direct register addressing, two registers operands are contained in registers r (rr) and d (rd). the result is stored in register d (rd). 13 at90s/ls4433 1042h?avr?04/03 i/o direct figure 12. i/o direct addressing operand address is contained in six bits of the instruction word. n is the destination or source register address. data direct figure 13. direct data addressing a 16-bit data address is contained in the 16 lsbs of a two-word instruction. rd/rr spec- ify the destination or source register. data indirect with displacement figure 14. data indirect with displacement operand address is the result of the y- or z-register contents added to the address con- tained in six bits of the instruction word. op rr/rd 16 31 15 0 16 lsbs $0000 $00df 20 19 data space data space $0000 $00df y or z - register op a n 0 0 5 6 10 15 15 14 at90s/ls4433 1042h?avr?04/03 data indirect figure 15. data indirect addressing operand address is the contents of the x-, y-, or the z-register. data indirect with pre- decrement figure 16. data indirect addressing with pre-decrement the x-, y-, or the z-register is decremented before the operation. operand address is the decremented contents of the x-, y-, or the z-register. data indirect with post- increment figure 17. data indirect addressing with post-increment the x-, y-, or the z-register is incremented after the operation. operand address is the content of the x-, y-, or the z-register prior to incrementing. data space $0000 $00df x, y, or z - register 0 15 data space $0000 $00df x, y, or z - register 0 15 -1 data space $0000 $00df x, y, or z - register 0 15 1 15 at90s/ls4433 1042h?avr?04/03 constant addressing using the lpm instruction figure 18. code memory constant addressing constant byte address is specified by the z-register contents. the 15 msbs select word address (0 - 2k), the lsb selects low byte if cleared (lsb = 0) or high byte if set (lsb = 1). indirect program addressing, ijmp and icall figure 19. indirect program memory addressing program execution continues at address contained by the z-register (i.e., the pc is loaded with the contents of the z-register). relative program addressing, rjmp and rcall figure 20. relative program memory addressing program execution continues at address pc + k + 1. the relative address k is from -2048 to 2047. $7ff $000 program memory $7ff $000 program memory $7ff $000 program memory +1 16 at90s/ls4433 1042h?avr?04/03 eeprom data memory the at90s4433 contains 256 by tes of data eeprom memory. it is organized as a sep- arate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles per location. the access between the eeprom and the cpu is descri bed on page 53, specifying the eeprom address reg- isters, the eeprom data register and the eeprom control register. for the spi data downloadin g, see page 93 for a deta iled description. the eeprom data memory is in-system programmable through the spi port. please refer to the ?eeprom read/write access? section on page 45 for a thorough description of eeprom access. memory access times and instruction execution timing this section describes the general access timing concepts for instruction execution and internal memory access. the avr cpu is driven by the system cloc k ?, directly generated from the external clock crystal for the chip. no in ternal clock division is used. figure 21 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit. figure 21. the parallel instruction fetches and instruction executions figure 22 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed and the result is stored back to the destination register. figure 22. single cycle alu operation the internal data sram access is performed in two system clock cycles as described in figure 23. system clock ? 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 system clock ? total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 17 at90s/ls4433 1042h?avr?04/03 figure 23. on-chip data sram access cycles i/o memory the i/o space definition of the at90s4433 is shown in table 2. system clock ? wr rd data data address address t1 t2 t3 t4 prev. address read write table 2. at90s4433 i/o space (1) i/o address (sram address) name function $3f ($5f) sreg status register $3d ($5d) sp stack pointer $3b ($5b) gimsk general interrupt mask register $3a ($5a) gifr general interrupt flag register $39 ($59) timsk timer/counter interrupt mask register $38 ($58) tifr timer/counter interrupt flag register $35 ($55) mcucr mcu general control register $34 ($54) mcusr mcu general status register $33 ($53) tccr0 timer/counter0 control register $32 ($52) tcnt0 timer/counter0 (8-bit) $2f ($4f) tccr1a timer/count er1 control register a $2e ($4e) tccr1b timer/counter1 control register b $2d ($4d) tcnt1h timer/counter1 high byte $2c ($4c) tcnt1l timer/counter1 low byte $2b ($4b) ocr1h timer/counter1 output compare register high byte $2a ($4a) ocr1l timer/counter1 output compare register low byte $27 ($47) icr1h timer/counter1 in put capture register high byte $26 ($46) icr1l timer/counter 1 in put capture register low byte $21 ($41) wdtcr watchdog timer control register $1e ($3e) eear eeprom address register $1d ($3d) eedr eeprom data register $1c ($3c) eecr eeprom control register $18 ($38) portb data register, port b 18 at90s/ls4433 1042h?avr?04/03 note: 1. reserved and unused locations are not shown in the table. all at90s4433 i/os and peripherals are placed in the i/o space. the i/o locations are accessed by the in and out instructions transferring data between the 32 general pur- pose working registers and the i/o space. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set section for more details. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o registers as sram, $20 must be added to this address. all i/o register addresses throughout this document are shown with the sram address in parentheses. for compatibility with future de vices, reserved bits should be written to zero when accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical ?1? to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with reg- isters $00 to $1f only. the i/o and peripherals control registers are explained in the following sections. $17 ($37) ddrb data direction register, port b $16 ($36) pinb input pins, port b $15 ($35) portc data register, port c $14 ($34) ddrc data direction register, port c $13 ($33) pinc input pins, port c $12 ($32) portd data register, port d $11 ($31) ddrd data direction register, port d $10 ($30) pind input pins, port d $0f ($2f) spdr spi i/o data register $0e ($2e) spsr spi status register $0d ($2d) spcr spi control register $0c ($2c) udr uart i/o data register $0b ($2b) ucsra uart control and status register a $0a ($2a) ucsrb uart control and status register b $09 ($29) ubrr uart baud rate register $08 ($28) acsr analog comparator control and status register $07 ($27) admux adc multiplexer select register $06 ($26) adcsr adc control and status register $05 ($25) adch adc data register high $04 ($24) adcl adc data register low $03 ($23) ubrrhi uart baud rate register high table 2. at90s4433 i/o space (1) (continued) i/o address (sram address) name function 19 at90s/ls4433 1042h?avr?04/03 status register ? sreg the avr status register (sreg) at i/o space location $3f ($5f) is defined as: bit 7 ? i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is clear ed (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred and is set by the reti instruction to enable subsequent interrupts. bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source and destination for the operated bit. a bit from a register in the register file can be cop- ied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetical operations. see the instruction set description for detailed information. bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s comple- ment overflow flag v. see the instruction set description for detailed information. bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the instruction set description for detailed information. bit 2 ? n: negative flag the negative flag n indicates a negative result from an arithmetical or logical operation. see the instruction set description for detailed information. bit 1 ? z: zero flag the zero flag z indicates a zero result from an arithmetical or logical operation. see the instruction set description for detailed information. bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetical or logical operation. see the instruction set description for detailed information. note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. this must be handled by software. bit 76543210 $3f ($5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 20 at90s/ls4433 1042h?avr?04/03 stack pointer ? sp the at90s4433 stack pointer is implemented as an 8-bit register in the i/o space loca- tion $3d ($5d). as the at90s4433 data memory has $0df locations, eight bits are used. the stack pointer points to the data sram stack area where the subroutine and inter- rupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above $60. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when an address is pushed onto the stack with subroutine calls and interrupts. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when an address is popped from the stack with return from subroutine ret or return from interrupt reti. reset and interrupt handling the at90s4433 provides 13 different interrupt sources. these interrupts and the sepa- rate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bi ts, which must be set (one) together with the i-bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 3. the list also determines the priority levels of the different interrupts. the lower the address, the higher the priority level. reset has the hi ghest priority, and next is int0 (the external interrupt request 0), etc. 76543210 $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 sp read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 3. reset and interrupt vectors vector no. program address source interrupt definition 1 $000 reset external pin, power-on reset, brown-out reset and watchdog reset 2 $001 int0 external interrupt request 0 3 $002 int1 external interrupt request 1 4 $003 timer1 capt timer/counter1 capture event 5 $004 timer1 comp timer/counter1 compare match 6 $005 timer1 ovf timer/counter1 overflow 7 $006 timer0 ovf timer/counter0 overflow 8 $007 spi, stc serial transfer complete 9 $008 uart, rx uart, rx complete 10 $009 uart, udre uart data register empty 11 $00a uart, tx uart, tx complete 12 $00b adc adc conversion complete 13 $00c ee_rdy eeprom ready 14 $00d ana_comp analog comparator 21 at90s/ls4433 1042h?avr?04/03 the most typical program setup for the reset and interrupt vector addresses are: address labels code comments $000 rjmp reset ; reset handler $001 rjmp ext_int0 ; irq0 handler $002 rjmp ext_int1 ; irq1 handler $003 rjmp tim1_capt ; timer1 capture handler $004 rjmp tim1_comp ; timer1 compare handler $005 rjmp tim1_ovf ; timer1 overflow handler $006 rjmp tim0_ovf ; timer0 overflow handler $007 rjmp spi_stc; ; spi transfer complete handler $008 rjmp uart_rxc ; uart rx complete handler $009 rjmp uart_dre ; udr empty handler $00a rjmp uart_txc ; uart tx complete handler $00b rjmp adc ; adc conversion complete interrupt handler $00c rjmp ee_rdy ; eeprom ready handler $00d rjmp ana_comp ; analog comparator handler ; $00e main: ldi r16,low(ramend); main program start $00f out sp,r16; $010 22 at90s/ls4433 1042h?avr?04/03 figure 24. reset logic note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling). table 4. reset characteristics (v cc = 5.0v) symbol parameter min typ max units v pot (1) power-on reset threshold voltage, rising 1.0 1.4 1.8 v power-on reset threshold voltage, falling 0.4 0.6 0.8 v v rst reset pin threshold voltage 0.6 v cc v v bot brown-out reset threshold voltage 2.2 (bodlevel=1) 2.7 (bodlevel=1) 3.0 (bodlevel=1) v 3.5 (bodlevel=0) 4.0 (bodlevel=0) 4.5 (bodlevel=0) mcu status register (mcusr) brown-out reset circuit power-on reset circuit boden bodlevel delay counters cksel[2:0] ck full wdrf borf extrf porf data b u s reset circuit watchdog timer on-chip rc oscillator counter reset internal reset reset v cc 23 at90s/ls4433 1042h?avr?04/03 note: 1. or external power-on reset. this table shows the start-up times from reset. from sleep, only the clock counting part of the start-up time is used . the watchdog oscillator is used for timing the real time part of the start-up time. the number wdt oscillator cycles used for each time-out is shown in table 6. the frequency of the watchdog oscillator is voltage dependent, as shown in the electri- cal characteristics section. power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detec- tion level is nominally 2.2v. the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as detect a fail- ure in supply voltage. the power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes a delay counter, which deter- mines the delay, for which the de vice is kept in reset after v cc rise. the time-out period of the delay counter is a combination of internal rc oscillator cycles and exter- nal oscillator cycles, and it can be defined by the user through the cksel fuses. the eight different selections for the delay period are presente d in table 5. the reset sig- nal is activated again, without any delay, when the v cc decreases to below detection level. table 5. reset delay selections cksel [2:0] start-up time, t tout at v cc = 2.7v start-up time, t tout at v cc = 5.0v recommended usage 000 16 ms + 6 ck 4 ms + 6 ck external clock, slowly rising power 001 6 ck 6 ck external clock, bod enabled (1) 010 256 ms + 16k ck 64 ms + 16k ck crystal oscillator 011 16 ms + 16k ck 4 ms + 16k ck crystal oscillator, fast rising power 100 16k ck 16k ck crystal oscillator, bod enabled (1) 101 256 ms + 1k ck 64 ms + 1k ck ceramic resonator 110 16 ms + 1k ck 4 ms + 1k ck ceramic resonator, fast rising power 111 1k ck 1k ck ceramic resonator, bod enabled (1) table 6. number of watchdog oscillator cycles time-out number of cycles 4.0 ms (at v cc = 5.0v) 4k 64 ms (at v cc = 5.0v) 64k 24 at90s/ls4433 1042h?avr?04/03 figure 25. mcu start-up, reset tied to v cc figure 26. mcu start-up, reset controlled externally external reset an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a rese t, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage (v rst ) on its positive edge, the delay timer starts the mcu after the time-out period (t tout ) has expired. figure 27. external reset during operation vcc reset time-out internal reset t tout v pot v rst vcc reset time-out internal reset t tout v pot v rst 25 at90s/ls4433 1042h?avr?04/03 brown-out detection at90s4433 has an on-chip brown-out detect ion (bod) circuit for monitoring the v cc level during the operation. the power supply must be decoupled with a 47 nf to 100 nf capacitor if the bod function is used. the bod circuit can be enabled/disabled by the fuse boden. when boden is e nabled (boden programmed), and v cc decreases to a value below the trigger level, the brown-ou t reset is immediately activated. when v cc increases above the trigger level, the brown-out reset is deactivated after a delay. the delay is defined by the user in the same way as the delay of por signal (see table 5). the trigger level for the bod can be selected by the fuse bodlevel to be 2.7v (bodlevel unprogrammed), or 4.0v (bodl evel programmed). the trigger level has a hysteresis of 50 mv to ensure spike-free brown-out detection. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than 3 s for trigger level 4.0v, 7 s for trigger level 2.7v (typical values). figure 28. brown-out reset during operation watchdog reset when the watchdog times out, it will generate a short rese t pulse of one xtal cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period (t tout ). see page 43 for details on operation of the watchdog. figure 29. watchdog reset during operation vcc reset time-out internal reset v bot- v bot+ t tout 26 at90s/ls4433 1042h?avr?04/03 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. bits 7..4 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is cleared by a power-on reset, or by writing a logical ?0? to the flag. bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bit is cleared by a power-on reset, or by writing a logical ?0? to the flag. bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. th e bit is cleared by a power-on reset, or by writing a logical ?0? to the flag. bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is cleared only by writing a logical ?0? to the flag. to make use of the reset flags to identify a reset condition, the user should read and then clear the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. interrupt handling the at90s4433 has two 8-bit interrupt mask control registers; gimsk (general inter- rupt mask) register and timsk (timer/counter interrupt mask) register. when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all inter- rupts are disabled. the user software can set (one) the i-bit to enable nested interrupts. the i-bit is set (one) when a return from interrupt instruction (reti) is executed. when the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. some of the interrupt flags can also be cleared by writing a logical ?1? to the flag bit position(s) to be cleared. if an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is e nabled or the flag is cleared by software. if one or more interrupt conditions occur w hen the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority. note that external level interrupt does not have a flag and will only be remembered for as long as the interrup t condition is active. bit 76543210 $34 ($54) ? ? ? ? wdrf borf extrf porf mcusr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 27 at90s/ls4433 1042h?avr?04/03 note that the status register is not automatically stored when entering an interrupt rou- tine or restored when returning from an interrupt routine. this must be handled by software. general interrupt mask register ? gimsk bit 7 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the mcu general control regist er (mcucr) defines whether the external interrupt is activated on rising or falling edge of the int1 pin or is level sensed. please note that intf1 flag is not set when the leve l-sensitive interrupt co ndition is met. how- ever, int1 interrupt is generated, provided that int1 mask bit is set in gimsk register. activity on the pin will cause an interrupt request even if int1 is configured as an output. the corresponding interrupt of external interrupt request 1 is executed from program memory address $002. see also ?external interrupts?. bit 6 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control regist er (mcucr) defines whether the external interrupt is activated on rising or falling edge of the int0 pin or is level sensed. please note that intf0 flag is not set when the leve l-sensitive interrupt co ndition is met. how- ever, int0 interrupt is generated, provided that int0 mask bit is set in gimsk register. activity on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is executed from program memory address $001. see also ?external interrupts?. bits 5..0 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. general interrupt flag register ? gifr bit 7 ? intf1: external interrupt flag1 when an edge on the int1 pin triggers an interrupt request, the corresponding interrupt flag, intf1 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int1 in gimsk, is set (one), the mcu will jump to the interrupt vector. the flag is always cleared when the interrupt routine is executed. alternatively, the flag is cleared by writing a logical ?1? to it. this fl ag is always cleared when int1 is configured as level interrupt. bit 7 6 5 4 3 2 1 0 $3b ($5b) int1 int0 ? ? ? ? ? ? gimsk read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $3a ($5a) intf1 intf0 ? ? ? ? ? ? gifr read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 28 at90s/ls4433 1042h?avr?04/03 bit 6 ? intf0: external interrupt flag0 when an edge on the int0 pin triggers an interrupt request, the corresponding interrupt flag, intf0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int0 in gimsk is set (one), the mcu will jump to the interrupt vector. the flag is always cleared when the interrupt routine is executed. alternatively, the flag is cleared by writing a logical ?1? to it. this fl ag is always cleared when int0 is configured as level interrupt. bits 5..0 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. timer/counter interrupt mask register ? timsk bit 7 ? toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $005) is executed if an overflow in timer/counter1 occurs, i.e., when the tov1 bit is set in the timer/counter interrupt flag register (tifr). bit 6 ? ocie1: timer/counter1 output compare match interrupt enable when the ocie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare match interrupt is enabled. the corresponding interrupt (at vector $004) is executed if a compare match in timer/counter1 occurs, i.e., when the ocf1 bit is set in the timer/counter interrupt flag register (tifr). bits 5, 4 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. bit 3 ? ticie1: timer/counter1 input capture interrupt enable when the ticie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 input capture event interrupt is enabled. the corresponding interrupt (at vector $003) is executed if a capture- triggering event occurs on pin 14, pb0 (icp), i.e., when the icf1 bit is set in the timer/counter interrupt flag register (tifr). bit 2 ? res: reserved bit this bit is a reserved bit in the at90s4433 and always reads as zero. bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $006) is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter interrupt flag register (tifr). bit 0 ? res: reserved bit this bit is a reserved bit in the at90s4433 and always reads as zero. bit 7 6 5 4 3 2 1 0 $39 ($59) toie1 ocie1 ? ? ticie1 ? toie0 ? timsk read/write r/w r/w r r r/w r r/w r initial value 0 0 0 0 0 0 0 0 29 at90s/ls4433 1042h?avr?04/03 timer/counter interrupt flag register ? tifr bit 7 ? tov1: timer/counter1 overflow flag the tov1 is set (one) when an overflow occurs in timer/counter1. tov1 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov1 is cleared by writing a logical ?1? to the flag. when the i-bit in sreg and toie1 (timer/counter1 overflow interrupt enable) and tov1 are set (one), the timer/counter1 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter1 advances from $0000. bit 6 ? ocf1: output compare flag 1 the ocf1 bit is set (one) when a compare match occurs between the timer/counter1 and the data in output compare register 1 (ocr1). ocf1 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf1 is cleared by writing a logical ?1? to the flag. when the i-bit in sreg and ocie1 (timer/counter1 compare match interrupt a enable) and the ocf1 are set (one), the timer/counter1 compare match interrupt is executed. bits 5, 4 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. bit 3 ? icf1: input capture flag 1 the icf1 bit is set (one) to flag an input capture event, indicating that the timer/counter1 value has been transferred to the input capture register (icr1). icf1 is cleared by hardware when executing th e corresponding interrupt handling vector. alternatively, icf1 is cleare d by writing a logical ?1? to the flag. when the sreg i-bit and ticie1 (timer/counter1 input capture interrupt enable) and icf1 are set (one), the timer/counter1 capture interrupt is executed. bit 2 ? res: reserved bit this bit is a reserved bit in the at90s4433 and always reads as zero. bit 1 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logical ?1? to the flag. when the sreg i-bit and toie0 (timer/counter0 overflow interrupt enable) and tov0 are set (one), the timer/counter0 overflow interrupt is executed. bit 0 ? res: reserved bit this bit is a reserved bit in the at90s4433 and always reads as zero. bit 7 6 5 4 3 2 1 0 $38 ($58) tov1 ocf1 ? ? icf1 ? tov0 ? tifr read/write r/w r/w r r r/w r r/w r initial value 0 0 0 0 0 0 0 0 30 at90s/ls4433 1042h?avr?04/03 external interrupts the external interrupts are triggered by the int1 and int0 pins. observe that, if enabled, the interrupts will trigger even if the int0/int1 pins are co nfigured as outputs. this feature provides a way of generating a software interrupt. the external interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the mcu control regist er (mcucr). when the ex ternal in terrupt is enabled and is configured as le vel triggered, the in terrupt will trigger as long as the pin is held low. the external interrupts are set up as described in the specification for the mcu control register (mcucr). interrupt response time the interrupt execution response for all the enabled avr interrupts is four clock cycles minimum. four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter (two bytes) is pushed onto the stack, and the stack pointer is decremented by two. the vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed befo re the interrupt is served. a return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. du ring these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two and the i-flag in sreg is set. when the avr exit s from an interrupt, it will always return to the main pro- gram and execute one more instruction before any pending interrupt is served. mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. bits 7, 6 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. bit 5 ? se: sleep enable the se bit must be set (one) to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid having the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended that the sleep enable se bit be set just before the execution of the sleep instruction. bit 4 ? sm: sleep mode this bit selects between the two available sleep modes. when sm is cleared (zero), idle mode is selected as sleep mode. when sm is set (one), power-down mode is selected as sleep mode. for details, refer to the paragraph ?sleep modes? below. bit 76543210 $35 ($55) ? ? se sm isc11 isc10 isc01 isc00 mcucr read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 31 at90s/ls4433 1042h?avr?04/03 bits 3, 2 ? isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the external pin int1 if the sreg i-flag and the corresponding interrupt mask in the gimsk are set. the level and edges on the external int1 pin that activate the interrupt are defined in table 7. the value on the int1 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. bits 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corresponding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 8. the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. sleep modes to enter the sleep mo des, the se bit in mcucr must be set (one) and a sleep instruc- tion must be executed. the sm bit in the mcucr register selects which sleep mode (idle or power-down) will be activated by the sleep instruction. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and i/o memory are unaltered. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. note that if a level-triggere d interrupt is used for wake-up from power-down, the low level must be held for a time longer than the reset delay time-out period (t tout ). other- wise, the device will not wake up. table 7. interrupt 1 sense control isc11 isc10 description 0 0 the low level of int1 generates an interrupt request. 0 1 any logical change on int1 generates an interrupt request. 1 0 the falling edge of int1 generates an interrupt request. 1 1 the rising edge of int1 generates an interrupt request. table 8. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 32 at90s/ls4433 1042h?avr?04/03 idle mode when the sm bit is cleared (zero), the sleep instruction fo rces the mcu into the idle mode stopping the cpu but allowing timer/counters, watchdog and the interrupt sys- tem to continue operating. this enables the mcu to wake up from external triggered interrupts as well as internal ones like timer overflow interrupt and watchdog reset. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and sta- tus register (acsr). this will reduce power consumption in idle mode. power-down mode when the sm bit is set (one), the sleep instruction forces the mcu into the power- down mode. in this mode, the external oscillator is stopped while the external interrupts and the watchdog (if enabled) continue opera ting. only an external reset, a watchdog reset (if enabled) or an external le vel interrupt can wake up the mcu. note that if a level-triggered interrupt is used for wake-up from power-down mode, the changed level must be held for a time to wake up the mcu. this makes the mcu less sensitive to noise. the wake-up period is equal to the clock-counting part of the reset period (see table 5). the mcu will wake up from power-down if the input has the required level for two watchdog oscillator cycles. if the wake-up period is shorter than two watchdog oscillator cycles, the mcu will wa ke up if the input has the required level for the duration of the wake-up period. if the wake-up condition disappears before the wake-up period has expired, the mcu will wake up from po wer-down without executing the corresponding interrupt. the period of the watchdog oscillator is 2.7 s (nominal) at 3.0v and 25 c. the fre- quency of the watchdog oscillator is voltage dependent as shown in the electrical characteristics section. when waking up from power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period. 33 at90s/ls4433 1042h?avr?04/03 timer/counters the at90s4433 provides two general purpose timer/counters ? one 8-bit t/c and one 16-bit t/c. timer/counters0 and 1 have indivi dual prescaling selection from the same 10-bit prescaling timer. these timer/count ers can either be used as a timer with an internal clock time base or as a counter with an external pin connection that triggers the counting. timer/counter prescaler figure 30. prescaler for timer/counter0 and 1 for timer/counters0 and 1, the four different prescaled selections are ck/8, ck/64, ck/256, and ck/1024, where ck is the oscillator clock. for the two timer/counters0 and 1, external source and stop can also be selected as clock sources. 8-bit timer/counter0 the 8-bit timer/counter0 can select clock source from ck, prescaled ck or an external pin. in addition, it can be stopped as de scribed in the specification for the timer/counter0 control register (tccr0). th e overflow status flag is found in the timer/counter interrupt flag register (tifr). control signals are found in the timer/counter0 control register (tccr0). the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask register (timsk). when timer/counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high resolution and a high-accuracy usage with the lower prescaling opportunities. similarly, the high prescaling opportunities make the timer/counter0 useful for lower speed functions or exact timing functions with infre- quent actions. figure 31 shows the block diagram for timer/counter0. tck1 tck0 34 at90s/ls4433 1042h?avr?04/03 figure 31. timer/counter0 block diagram timer/counter0 control register ? tccr0 bits 7 ? 3 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. bits 2, 1, 0 ? cs02, cs01, cs00: clock select0, bits 2, 1, and 0 the clock select0 bits 2, 1, and 0 define the prescaling source of timer/counter0. ocie1 ocf1 t0 bit 7 6 5 4 3 210 $33 ($53) ? ? ? ? ? cs02 cs01 cs00 tccr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 9. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, timer/counter0 is stopped. 001ck 010ck/8 011ck/64 1 0 0 ck/256 1 0 1 ck/1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge 35 at90s/ls4433 1042h?avr?04/03 the stop condition provides a timer enable/disable function. the prescaled ck modes are scaled directly from the ck oscillator clock. if the exte rnal pin modes are used for timer/counter0, transitions on pd4/(t0) will clock the counter even if the pin is config- ured as an output. this feature can give the user software control of the counting. timer counter0 ? tcnt0 the timer/counter0 is realized as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues counting in the clock cycle fo llowing the write operation. 16-bit timer/counter1 figure 32 shows the block diagram for timer/counter1. figure 32. timer/counter1 block diagram the 16-bit timer/counter1 can select clock source from ck, prescaled ck or an exter- nal pin. in addition, it can be stopped as described in the specification for the timer/counter1 control regist er (tccr1a). the different status flags (overflow, com- pare match and capture event) and control signals are found in the timer/counter bit 76543210 $32 ($52) msb lsb tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 t1 36 at90s/ls4433 1042h?avr?04/03 interrupt flag register (tifr). the interrupt enable/disable settings for timer/counter1 are found in the timer/counter interrupt mask register (timsk). when timer/counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 16-bit timer/counter1 features both a high resolution and a high-accuracy usage with the lower prescaling opportunities. si milarly, the high prescaling opportunities makes the timer/counter1 useful for lowe r speed functions or exact timing functions with infrequent actions. the timer/counter1 supports an output compare function using the output compare register1 (ocr1) as the data source to be compared to the timer/counter1 contents. the output compare functions include optional clearing of the counter on compare matches and actions on the output compare pin 1 on compare matches. timer/counter1 can also be used as a 8-, 9-, or 10-bit pulse width modulator. in this mode, the counter and the ocr1 register serve as a glitch-free, stand-alone pwm with centered pulses. refer to page 41 for a detailed description of this function. the input capture function of timer/counter1 provides a capture of the timer/counter1 contents to the input capture register (icr1), triggered by an external event on the input capture pin (icp). the actual capture event settings are defined by the timer/counter1 control register (tccr1). in addition, the analog comparator can be set to trigger the input capture. refer to the section, ?the analog comparator?, for details of this. the icp pin logic is shown in figure 33. figure 33. icp pin schematic diagram if the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the capture flag. the input pin signal is sampled at xtal clock frequency. 37 at90s/ls4433 1042h?avr?04/03 timer/counter1 control register a ? tccr1a bits 7, 6 ? com11, com10: compare output mode1, bits 1, and 0 the com11 and com10 control bits dete rmine any output pin action following a compare match in timer/counter1. any output pin actions affect pin oc1 (output compare pin 1). this is an alternative function to an i/o port, and the corresponding direction control bit must be set (one) to control an output pin. the control configuration is shown in table 10. in pwm mode, these bits have a different function. refer to table 11 for a detailed description. bits 5..2 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. bits 1, 0 ? pwm11, pwm10: pulse width modulator select bits these bits select pwm operation of timer/c ounter1 as specified in table 11. this mode is described on page 41. bit 7 6 5 4 3 2 1 0 $2f ($4f) com11 com10 ? ? ? ? pwm11 pwm10 tccr1a read/write r/w r/w r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 10. compare 1 mode select com11 com10 description 0 0 timer/counter1 disconnected from output pin oc1 0 1 toggle the oc1 output line. 1 0 clear the oc1 output line (to zero). 1 1 set the oc1 output line (to one). table 11. pwm mode select pwm11 pwm10 description 0 0 pwm operation of timer/counter1 is disabled 0 1 timer/counter1 is an 8-bit pwm 1 0 timer/counter1 is a 9-bit pwm 1 1 timer/counter1 is a 10-bit pwm 38 at90s/ls4433 1042h?avr?04/03 timer/counter1 control register b ? tccr1b bit 7 ? icnc1: input captur e1 noise canceler (4 cks) when the icnc1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. the input capture is triggered at the firs t rising/falling edge sampled on the icp (input capture pin) as specified. when the icnc1 bit is set (one), four successive samples are measured on the icp (input capture pin), and all samples must be high/low according to the input capture trigger specification in the ices1 bit. the actual sampling frequency is t he xtal clock frequency. bit 6 ? ices1: input capture1 edge select while the ices1 bit is cleared (zero), the timer/counter1 contents are transferred to the input capture register (icr1) on the falling edge of the input capture pin (icp). while the ices1 bit is set (one), the timer/counter1 contents are transferred to the input cap- ture register (icr1) on the rising edge of the input capture pin (icp). bits 5, 4 ? res: reserved bits these bits are reserved bits in the at90s4433 and always read as zero. bit 3 ? ctc1: clear timer/counter1 on compare match when the ctc1 control bit is set (one), the timer/counter1 is reset to $0000 in the clock cycle after a compare match. if the ctc1 control bit is cleared, timer/counter1 contin- ues counting and is unaffected by a co mpare match. since the compare match is detected in the cpu clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. when a prescaling of 1 is used and the compare regi ster is set to c, the timer will count as follows if ctc1 is set: ... | c-2 | c-1 | c | 0 | 1 | ... when the prescaler is set to divide by 8, the timer will count like this: ... | c-2, c-2, c-2, c-2, c-2, c-2, c-2, c-2 | c-1, c-1, c-1, c-1, c-1, c-1, c-1, c-1 | c, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 1, 1| ... in pwm mode, this bit has no effect. bit 7 6 5 4 3 2 1 0 $2e ($4e) icnc1 ices1 ? ? ctc1 cs12 cs11 cs10 tccr1b read/write r/w r/w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 39 at90s/ls4433 1042h?avr?04/03 bits 2, 1, 0 ? cs12, cs11, cs10: clock select1, bits 2, 1, and 0 the clock select1 bits 2, 1, and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable function. the prescaled ck modes are scaled directly from the ck oscillator clock. if the exte rnal pin modes are used for timer/counter0, transitions on pd5/(t1) will clock the counter even if the pin is config- ured as an output. this feature can give the user software control of the counting. timer/counter1 ? tcnt1h and tcnt1l this 16-bit register contains the presca led value of the 16-bit timer/counter1. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary regis- ter (temp). this temporary register is also used when accessing ocr1 and icr1. if the main program and interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allo wed from within in terrupt routines). tcnt1 timer/counter1 write when the cpu writes to the high byte tcnt1h, the written data is placed in the temp register. next, when the cpu writes the low byte tcnt1l, this byte of data is com- bined with the byte data in the temp register, and all 16 bits are written to the tcnt1 timer/counter1 register simultaneously. consequently, the high byte tcnt1h must be accessed first for a full 16-bit register write operation. tcnt1 timer/counter1 read when the cpu reads the low byte tcnt1l, the data of the low byte tcnt1l is sent to the cpu and the data of the high byte tcnt1h is placed in the temp register. when the cpu reads the data in the high byte tcnt1h, the cpu receives the data in table 12. clock 1 prescale select cs12 cs11 cs10 description 0 0 0 stop, the timer/counter1 is stopped. 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 1 1 0 external pin t1, falling edge 1 1 1 external pin t1, rising edge bit 151413121110 9 8 $2d ($4d) msb tcnt1h $2c ($4c) lsb tcnt1l 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/wr/wr/wr/wr/wr/wr/wr/w initial value 0 0 0 0 0 0 0 0 00000000 40 at90s/ls4433 1042h?avr?04/03 the temp register. consequently, the low byte tcnt1l must be accessed first for a full 16-bit register read operation. the timer/counter1 is realized as an up or up/down (in pwm mode) counter with read and write access. if timer/counter1 is written to and a clock source is selected, the timer/counter1 continues countin g in the timer clock cycle after it is preset with the writ- ten value. timer/counter1 output compare register ? ocr1h and ocr1l the output compare register is a 16-bit read/write register. the timer/counter1 output compare regist er contains the data to be continuously compared with timer/counter1. actions on compare matches are specified in the timer/counter1 control and status register. since the output compare register (ocr1) is a 16-bit register, a temporary register temp is used when ocr1 is written to ensure that both bytes are updated simulta- neously. when the cpu writes the high byte, ocr1h, the data is temporarily stored in the temp register. when the cpu writes the low byte, ocr1l, the temp register is simultaneously written to ocr1h. consequently, the high byte ocr1h must be written first for a full 16-bit register write operation. the temp register is also used when accessing tcnt1 and icr1. if the main program and interrupt routines perform access to registers using temp, interrupts must be dis- abled during access from the main program. bit 151413121110 9 8 $2b ($4b) msb ocr1h $2a ($4a) lsb ocr1l 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/wr/wr/wr/wr/wr/wr/wr/w initial value 0 0 0 0 0 0 0 0 00000000 41 at90s/ls4433 1042h?avr?04/03 timer/counter1 input capture register ? icr1h and icr1l the input capture register is a 16-bit, read only register. when the rising or falling edge (according to the input capture edge setting [ices1]) of the signal at the input capture pin (icp) is detected, the current value of the timer/counter1 is transferred to the input ca pture register (icr1). at the same time, the input capture flag (icf1) is set (one). since the input capture register (icr1) is a 16-bit register, a temporary register (temp) is used when icr1 is read to ensure that both bytes are read simultaneously. when the cpu reads the low byte, icr1l, the data is sent to the cpu and the data of the high byte, icr1h, is placed in the temp register. when the cpu reads the data in the high byte, icr1h, the cpu receives th e data in the temp register. consequently, the low byte, icr1l, must be accessed first for a full 16-bit register read operation. the temp register is also used when accessing tcnt1 and ocr1. if the main pro- gram and interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program. timer/counter1 in pwm mode when the pwm mode is selected, timer/counter1 and the output compare register1 (ocr1) form a 8-, 9-, or 10-bit, free-running, glitch-free, phase correct pwm with output on the pb1(oc1) pin. timer/counter1 acts as an up/down counter, counting up from $0000 to top (see table 13), where it turns and counts down again to zero before the cycle is repeated. when the counter value matc hes the contents of the 8, 9, or 10 least significant bits of ocr1, the pb1(oc1) pin is set or cleared according to the settings of the com11 and com10 bits in the timer/counter1 control register (tccr1). refer to table 14 for details. note: 1. if the compare register contains t he top value and the prescaler is not in use (cs12..cs10 = 001), the pwm output will not produce any pulse at all, because the up-counting and down-counting values are reached simultaneously. when the pres- caler is in use (cs12..cs10 001 or 000), the pwm output goes active when the counter reaches the top value, but the do wn-counting compare match is not inter- preted to be reached before the next time the counter reaches the top value, making a one-period pwm pulse. bit 151413121110 9 8 $27 ($47) msb icr1h $26 ($46) lsb icr1l 76543210 read/writerrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 table 13. timer top values and pwm frequency (1) pwm resolution timer top value frequency 8-bit $00ff (255) f tck1 /510 9-bit $01ff (511) f tck1 /1022 10-bit $03ff(1023) f tck1 /2046 42 at90s/ls4433 1042h?avr?04/03 note that in the pwm mode, the ten least significant ocr1 bits, when written, are trans- ferred to a temporary location. they are latched when timer/counter1 reaches top. this prevents the occurrence of odd-length pwm pulses (glitches) in the event of an unsynchronized ocr1 write. see figure 34 for an example. figure 34. effects on unsynchronized ocr1 latching during the time between the write and the latch operation, a read from ocr1 will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1. when ocr1 contains $0000 or top, the outpu t oc1 is updated to low or high on the next compare match according to the settings of com11 and com10. this is shown in table 15. in pwm mode, the timer overflow flag1 (tov1) is set when the counter changes direc- tion at $0000. timer overflow interrupt1 operates exactly as in normal timer/counter mode, i.e., it is executed when tov1 is set, provided that timer overflow interrupt1 and global interrupts are enabled. this also applies to the timer output compare1 flag and interrupt. table 14. compare1 mode select in pwm mode com11 com10 effect on oc1 0 0 not connected 0 1 not connected 10 cleared on compare match, up-count ing. set on compare match, down- counting (non-inverted pwm). 11 cleared on compare match, down-c ounting. set on compare match, up- counting (inverted pwm). table 15. pwm outputs ocr = $0000 or top com11 com10 ocr1 output oc1 1 0 $0000 l 10top h 1 1 $0000 h 11top l 43 at90s/ls4433 1042h?avr?04/03 watchdog timer the watchdog timer is clocked from a separat e on-chip oscillator. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 6. see characterization data for typical values at other v cc levels. the wdr (watchdog reset) instruction resets the watchdog timer. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the at90s4433 rese ts and executes from the reset vector. for timing details on the watchdog reset, refer to page 25. to prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. refer to the description of the watchdog timer control register for details. figure 35. watchdog timer watchdog timer control register ? wdtcr bits 7..5 ? res: reserved bits these bits are reserved bits in the at90s4433 and will always read as zero. bit 4 ? wdtoe: watchdog turn-off enable this bit must be set (one) when the wde bit is cleared. otherwise, the watchdog will not be disabled. once set, hardware will clear this bit to zero after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. bit 3 ? wde: watchdog enable when the wde is set (one), the watchdog timer is enabled; if the wde is cleared (zero), the watchdog timer function is disabled. wde can only be cleared if the wdtoe bit is set (one). to disable an enabled watchdog timer, the following proce- dure must be followed: 1. in the same operation, write a logical ?1? to wdtoe and wde. a logical ?1? must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logical ?0? to wde. this disables the watchdog. bit 76543210 $21 ($41) ? ? ? wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 44 at90s/ls4433 1042h?avr?04/03 bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1, and 0 the wdp2, wdp1, and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown intable 16. note: 1. the frequency of the watchdog oscillato r is voltage dependent, as shown in the electrical charac teristics section. the wdr (watchdog reset) instruction should always be executed before the watchdog timer is enabled. this ensures th at the reset period will be in accordance with the watchdog timer prescale settings . if the watchdog timer is enabled without reset, the watchdog timer may not start counting from zero. to avoid unintentional mcu reset, the watchdog timer should be disabled or reset before changing the watchdog timer prescale select. table 16. watchdog timer prescale select (1) wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k cycles 47 ms 15 ms 0 0 1 32k cycles 94 ms 30 ms 0 1 0 64k cycles 0.19 s 60 ms 0 1 1 128k cycles 0.38 s 0.12 s 1 0 0 256k cycles 0.75 s 0.24 s 1 0 1 512k cycles 1.5 s 0.49 s 1 1 0 1,024k cycles 3.0 s 0.97 s 1 1 1 2,048k cycles 6.0 s 1.9 s 45 at90s/ls4433 1042h?avr?04/03 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time is in the range of 2.5 - 4 ms, depending on the v cc voltages. a self-timing function lets the user software detect when the next byte can be written. a special eeprom ready interrupt can be set to trigger when the eeprom is ready to accept new data. an ongoing eeprom write operation will comple te even if a reset condition occurs. in order to prevent unintentional eeprom writes, a two-state write procedure must be followed. refer to the description of the eep rom control register for details on this. when the eeprom is written, the cpu is ha lted for two clock cycles before the next instruction is executed. when the eeprom is read, the cpu is halt ed for four clock cycles before the next instruction is executed. eeprom address register ? eear the eeprom address register (eear) specifies the eeprom address in the 256 bytes of eeprom space. th e eeprom data bytes are add ressed linearly between 0 and 255. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. eeprom data register ? eedr bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address gi ven by the eear register. for the eeprom read oper- ation, the eedr contains the data read out from the eeprom at the address given by eear. eeprom control register ? eecr bits 7..4 ? res: reserved bits these bits are reserved bits in the at90s4433 and will always read as zero. bit 76543210 $1e ($3e) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eear read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x bit 76543210 $1d ($3d) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $1c ($3c) ????eerieeemweeeweeereeecr read/write r r r r r/w r/w r/w r/w initial value00000000 46 at90s/ls4433 1042h?avr?04/03 bit 3 ? eerie: eeprom ready interrupt enable when the i-bit in sreg and eerie are set (one), the eeprom ready interrupt is enabled. when cleared (zero), the interrupt is disabled. the eeprom ready interrupt generates a constant interrupt when eewe is cleared (zero). bit 2 ? eemwe: eeprom master write enable the eemwe bit determines w hether setting eewe to one causes the eeprom to be written. when eemwe is set (one), setting eewe will write data to the eeprom at the selected address. if eemwe is zero, setti ng eewe will have no effect. when eemwe has been set (one) by so ftware, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for a eeprom write procedure. bit 1 ? eewe: eeprom write enable the eeprom write enable si gnal (eewe) is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be set to write the value into the eeprom. the eemwe bit must be set when the logical ?1? is written to eewe, oth- erwise no eeprom write takes place. t he following procedure should be followed when writing the eeprom (the order of steps 2 and 3 is unessential): 1. wait until eewe becomes zero. 2. write new eeprom addr ess to eear (optional). 3. write new eeprom data to eedr (optional). 4. write a logical ?1? to the eemwe bit in ee cr (to be able to write a logical ?1? to the eemwe bit, the eewe bit must be written to zero in the same cycle). 5. within four clock cycles after setting eemwe, write a logical ?1? to eewe. caution : an interrupt between step 4 and step 5 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting an other eeprom access, the eear and eedr registers will be modified, causing the inte rrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during the last four steps to avoid these problems. when the write access time (typically 2.5 ms at v cc = 5v or 4 ms at v cc = 2.7v) has elapsed, the eewe bit is cleared (zero) by hardware. the user software can poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. bit 0 ? eere: eeprom read enable the eeprom read enable signal (eere) is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be set. when the eere bit is cleared (zero) by hardware, requested data is found in the eedr register. the eeprom read access takes one instruction and there is no need to poll the eere bit. when eere has been set, the cpu is halted for four cycles before the next instruc- tion is executed. the user should poll the eewe bit before starting the read operation. if a write operation is in progress when new data or address is written to the eeprom i/o registers, the write operation will be in terrupted and the re sult is undefined. 47 at90s/ls4433 1042h?avr?04/03 prevent eeprom corruption during periods of low v cc , the eeprom data can be corrup ted because the supply volt- age is too low for the cpu and the eeprom to operate prope rly. these issues are the same as for board-level systems using the eeprom, and the same design solutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the eeprom requires a minimum voltage to operate correctly. second, the cpu itself can execute instructions incorrectly if the sup- ply voltage for executing instructions is too low. eeprom data corruption can easily be avoi ded by following thes e design recommen- dations (one is sufficient): 1. keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating speed matches the detection level. if not, an external low v cc reset protection circuit can be applied. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to de code and execute instructions, effec- tively protecting the eeprom registers from unintentional writes. 3. store constants in flash memory if the ability to change memory contents from software is not required. flash memory cannot be up dated by the cpu and will not be subject to corruption. 48 at90s/ls4433 1042h?avr?04/03 serial peripheral interface ? spi the serial peripheral interface (spi) allows high-speed synchronous data transfer between the at90s4433 and peripheral devices or between several avr devices. the at90s4433 spi features include the following: full duplex, three-wire synchronous data transfer master or slave operation lsb first or msb first data transfer four programmable bit rates end of transmission interrupt flag write collision flag protection wake-up from idle mode figure 36. spi block diagram the interconnection between master and slav e cpus with spi is shown in figure 37. the pb5(sck) pin is the clock output in the master mode and is the clock input in the slave mode. writing to the spi data register of the master cpu starts the spi clock generator, and the data written shifts out of the pb3(mosi) pin and into the pb3(mosi) pin of the slave cpu. after shifting one byte, the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the slave select input, pb2(ss ), is set low to select an individual slave spi device. the two shift registers in the master and the slave can be considered as one distributed 16-bi t circular shift register. this is shown in figure 37. when data is shifted from the master to the slave, data is also shifted in the opposite direction, simultaneously. this means that during one shift cycle, data in the master and the slave are interchanged. 49 at90s/ls4433 1042h?avr?04/03 figure 37. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direction. this means that bytes to be tr ansmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received byte must be read from the spi data register before the next byte has been completely shifted in. otherwise, the first byte is lost. when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 17. note: 1. see ?alternate functions of port b? on page 73 for a detailed description of how to define the direction of the user-defined spi pins. ss pin functionality when the spi is configured as a master (mstr in spcr is set), the user can determine the direction of the ss pin. if ss is configured as an output, the pin is a general output pin, which does not affect the spi system. if ss is configured as an input, it must be held high to ensure master spi operation. if the ss pin is driven low by peripheral circuitry when the spi is configured as master with the ss pin defined as an input, the spi sys- tem interprets this as another master selecting the spi as a slave and starts to send data to it. to avoid bus contention, the spi system takes the following actions: 1. the mstr bit in spcr is cleared and the spi system becomes a slave. as a result of the spi becoming a slave, the mosi and sck pins become inputs. 2. the spif flag in spsr is set, and if the spi interrupt is enab led and the i-bit in sreg is set, the interrup t routine will be executed. thus, when interrupt-driven spi transmittal is used in master mode, and there exists a possibility that ss is driven low, the interrupt shoul d always check that the mstr bit is still set. once the mstr bit has been cleared by a slave select, it must be set by the user to re-enable the spi master mode. when the spi is configured as a slave, the ss pin is always input. when ss is held low, the spi is activated and miso becomes an output if configured so by the user. all other table 17. spi pin direction overrides (1) pin direction overrides, master spi mo de direction overrides, slave spi modes mosi user defined input miso input user defined sck user defined input ss user defined input 50 at90s/ls4433 1042h?avr?04/03 pins are inputs. when ss is driven high, externally all pins are inputs and the spi is passive, which means that it will not receive incoming data. note that the spi logic will be reset once the ss pin is brought high. if the ss pin is brought high during a transmission, the spi will stop sending and receiving immediately and both data received and data sent must be considered as lost. data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 38 and figure 39. figure 38. spi transfer format with cpha = 0 and dord = 0 figure 39. spi transfer format with cpha = 1 and dord = 0 51 at90s/ls4433 1042h?avr?04/03 spi control register ? spcr bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be execut ed if spif bit in the spsr register is set and the global interrupts are enabled. bit 6 ? spe: spi enable when the spe bit is set (one), the spi is enabled. this bit mu st be set to enable any spi operations. bit 5 ? dord: data order when the dord bit is set (one), the lsb of the data word is transmitted first. when the dord bit is cleared (zero), the msb of the data word is transmitted first. bit 4 ? mstr: master/slave select this bit selects master spi mode when set (one), and slave spi mode when cleared (zero). if ss is configured as an input and is dr iven low while mstr is set, mstr will be cleared and spif in spsr will beco me set. the user will then have to set mstr to re- enable spi master mode. bit 3 ? cpol: clock polarity when this bit is set (one), sck is high when idle. when cpol is cleared (zero), sck is low when idle. refer to figure 38 and figure 39 for additional information. bit 2 ? cpha: clock phase refer to figure 38 or figure 39 for the functionality of this bit. bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency (f cl ) is shown in table 18. bit 76543210 $0d ($2d) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 18. relationship between sck an d the oscillator frequency spr1 spr0 sck frequency 00 f cl /4 01 f cl /16 10 f cl /64 11 f cl /128 52 at90s/ls4433 1042h?avr?04/03 spi status register ? spsr bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif bit is set (one) and an interrupt is gener- ated if spie in spcr is set (one) and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware when executing the corr esponding interrupt handling vector. alter- natively, the spif bit is cleared by first reading the spi status register with spif set (one), then by accessing the spi data register (spdr). bit 6 ? wcol: write collision flag the wcol bit is set if the spi data regist er (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared (zero) by first reading the spi status reg- ister with wcol set (one), and then by accessing the spi data register. bits 5..0 ? res: reserved bits these bits are reserved bits in the at90s4433 and will always read as zero. the spi interface on the at90s4433 is also used for program memory and eeprom downloading or uploading. see page 93 for serial programming and verification. spi data register ? spdr the spi data register is a read/write register used for data transfer between the regis- ter file and the spi shift register. writing to the register initiates data transmission. reading the register causes the shift register receive buffer to be read. bit 76543210 $0e ($2e) spif wcol ? ? ? ? ? ? spsr read/writerrrrrrrr initial value00000000 bit 76543210 $0f ($2f) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined 53 at90s/ls4433 1042h?avr?04/03 uart the at90s4433 features a full duplex (separate receive and transmit registers) uni- versal asynchronous receiver and transmitter (uart). the main features are: baud rate generator generates any baud rate high baud rates at low xtal frequencies 8 or 9 bits data noise filtering overrun detection framing error detection false start bit detection three separate interrupts on tx complete, tx data register empty, and rx complete multi-processor communication mode data transmission a block schematic of the uart tran smitter is shown in figure 40. figure 40. uart transmitter data transmission is initiated by writing the data to be transmitted to the uart i/o data register (udr). data is transferred from udr to the transmit shift register when: a new character has been written to udr after the stop bit from the previous character has been shifted out. the shift register is loaded immediately. a new character has been written to udr before the stop bit from the previous character has been shifted out. the shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. when data is transferred from udr to the shift register, the udre (uart data regis- ter empty) bit in the uart control and status register a, ucsra, is set. when this bit is set (one), the uart is ready to receive the next character. at the same time as the uart control and staus register b (ucsrb) uart control and staus register a (ucsra) 54 at90s/ls4433 1042h?avr?04/03 data is transferred from udr to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (sto p bit). if 9-bit data word is selected (the chr9 bit in the uart control and status register b, ucsrb is set), the txb8 bit in ucsrb is transferred to bit nine in the transmit shift register. on the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the txd pin. then follows the data, lsb first. when the stop bit has been shifted out, the shift register is loaded if any new data has been written to the udr during the transmission. during loading, udr e is set. if there is no new data in the udr register to send when the stop bit is shifted out, the udre flag will remain set until udr is written again. when no new data has been written, and the stop bit has been present on txd for one bit length, the tx complete flag, txc, in ucsra is set. the txen bit in ucsrb enables the uart tran smitter when set (one). when this bit is cleared (zero), the pd1 pin can be used for general i/o. when txen is set, the uart transmitter will be connected to pd1, which is forced to be an output pin regardless of the setting of the ddd1 bit in ddrd. data reception figure 41 shows a block diagram of the uart receiver. figure 41. uart receiver uart control and staus register b (ucsrb) uart control and staus register a (ucsra) 55 at90s/ls4433 1042h?avr?04/03 the receiver front-end logic samples the signal on the rxd pin at a frequency 16 times the baud rate. while the line is idle, one single sample of lo gical ?0? will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. let sample 1 denote the first zero-sample. following the 1-to-0 transition, the receiver samples the rxd pin at samples 8, 9, and 10. if two or more of these three samples are found to be logical ?1?s, the start bit is rejected as a noi se spike and the receiver starts looking for the next 1-to-0 transition. if, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. these bits are also sampled at samples 8, 9, and 10. the logical value found in at least two of the three samples is taken as the bit value. all bits are shifted into the transmitter shift register as they are sa mpled. sampling of an incoming character is shown in figure 42. figure 42. sampling received data when the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. if two or more samples are logical ?0?s, the framing error (fe) flag in the uart control and status register a (ucsra) is set. before reading the udr register, the user should always check the fe bit to detect framing errors. whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to udr and the rxc flag in ucsra is set. udr is, in fact, two phys- ically separate registers: one for transmitted data and one for received data. when udr is read, the receive data register is accessed, and when udr is written, the transmit data register is accessed. if 9-bit da ta word is selected (the chr9 bit in the uart control and status register b, ucsrb is set), the rxb8 bit in ucsrb is loaded with bit nine in the transmit shift register when data is transferred to udr. if, after having received a character, the udr register has not been read since the last receive, the overrun (or) flag in ucsrb is set. this means that the last data byte shifted into the shift register could not be transferred to udr and has been lost. the or bit is buffered and is updated when the valid data byte in udr is read. thus, the user should always check the or bit after re ading the udr register in order to detect any overruns if the baud rate is high or cpu load is high. when the rxen bit in the ucsrb register is cleared (zero), the receiver is disabled. this means that the pd0 pin can be used as a general i/o pin. when rxen is set, the uart receiver will be connected to pd0, whic h is forced to be an input pin regardless of the setting of the ddd0 bit in ddrd. when pd 0 is forced to input by the uart, the portd0 bit can still be used to contro l the pull-up resi stor on the pin. when the chr9 bit in the ucsrb register is set, transmitted and received characters are nine bits long, plus start and stop bits. the ninth data bit to be transmitted is the txb8 bit in ucsrb register. this bit must be set to the wanted value before a trans- mission is initiated by writing to the udr re gister. the ninth data bit received is the rxb8 bit in the ucsrb register. 56 at90s/ls4433 1042h?avr?04/03 multi-processor communication mode the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address byte to find out which mcu has been addressed. if a particular slav e mcu has been addressed, it will receive the following data bytes as no rmal, while the other slave mc us will ignore the data bytes until another address byte is received. for an mcu to act as a master mcu, it should enter 9-bit transmission mode (chr9 in ucsrb set). the ninth bit must be one to indicate that an address byte is being trans- mitted, and zero to indicate that a data byte is being transmitted. for the slave mcus, the mechanism appears slightly differently for 8-bit and 9-bit reception mode. in 8-bit reception mode ( chr9 in ucsrb cleared), the stop bit is one for an address byte and zero for a data byte. in 9-bit reception mode (chr9 in ucsrb set), the ninth bit is one for an address byte and zero for a data byte, whereas the stop bit is always high. the following procedure should be used to exchange data in multi-processor communi- cation mode: 1. all slave mcus are in multi-proces sor communication mode (mpcm in ucsra is set). 2. the master mcu sends an address byte, and all slaves receive and read this byte. in the slave mcus, the rxc flag in ucsra will be set as normal. 3. each slave mcu reads the udr regist er and determines if it has been selected. if so, it clears the mpcm bit in ucsra, otherwise it waits for the next address byte. 4. for each received data byte, the rece iving mcu will set the receive complete flag (rxc in ucsra). in 8-bit mode, the receiving mcu will also generate a framing error (fe in ucsra set), since the stop bit is zero. the other slave mcus, which still have the mpcm bit set, will ignore the data byte. in this case, the udr register and the rxc or fe flags will not be affected. 5. after the last byte has been transferred, the process repeats from step 2. 57 at90s/ls4433 1042h?avr?04/03 uart control uart i/o data register ? udr the udr register is actually two physicall y separate registers sharing the same i/o address. when writing to the register, the uart transmit data register is written. when reading from udr, the uart receive data register is read. uart control and status register a ? ucsra bit 7 ? rxc: uart receive complete this bit is set (one) when a received character is transferred from the receiver shift register to udr. the bit is set regardless of any detected framing errors. when the rxcie bit in ucsrb is set, the uart re ceive complete interrupt will be executed when rxc is set (one). rxc is cleared by reading udr. when in terrupt-driven data reception is used, the uart receive comp lete interrupt routi ne must read udr in order to clear rxc, otherwise a new interr upt will occur once the interrupt routine terminates. bit 6 ? txc: uart transmit complete this bit is set (one) when the entire charac ter (including the stop bit) in the transmit shift register has been shifted out and no new data has been written to udr. this flag is especially useful in ha lf-duplex communications interfaces, where a transmitting appli- cation must enter receive mode and free the communications bus immediately after completing the transmission. when the txcie bit in ucsrb is set, settin g of txc causes the uart transmit com- plete interrupt to be executed. txc is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the txc bit is cleared (zero) by writing a logical ?1? to the bit. bit 5 ? udre: uart data register empty this bit is set (one) when a character written to udr is transferred to the transmit shift register. setting of this bit indicates that the transmitter is ready to receive a new char- acter for transmission. when the udrie bit in ucsrb is set, the ua rt transmit complete interrupt to be exe- cuted as long as udre is set. udre is clea red by writing udr. when interrupt-driven data transmittal is used, the uart data register empty interrupt routine must write udr in order to clear udre, otherwise a new interrupt will occur once the interrupt rou- tine terminates. udre is set (one) during reset to indicate that the transmitter is ready. bit 76543210 $0c ($2c) msb lsb udr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $0b ($2b) rxc txc udre fe or ? ? mpcm ucsra read/write r r/w r r r r r r/w initial value00100000 58 at90s/ls4433 1042h?avr?04/03 bit 4 ? fe: framing error this bit is set if a framing error condition is detected, i.e., when the stop bit of an incom- ing character is zero. the fe bit is cleared when the stop bit of received data is one. bit 3 ? or: overrun this bit is set if an overrun condition is detected, i.e., when a character already present in the udr register is not read before the next character has b een shifted into the receiver shift register. the or bit is buffere d, which means that it will be set once the valid data still in udre is read. the or bit is cleared (zero) when da ta is received and transferred to udr. bits 2..1 ? res: reserved bits these bits are reserved bits in the at90s4433 and will always read as zero. bit 0 ? mpcm: multi-processor communication mode this bit is used to enter multi-processor communication mode. the bit is set when the slave mcu waits for an address byte to be received. when the mcu has been addressed, the mcu switches off the mpcm bit and starts data reception. for a detailed description, see ?multi-processor communication mode?. uart control and status register b ? ucsrb bit 7 ? rxcie: rx complete interrupt enable when this bit is set (one), a setting of the rxc bit in ucsra will cause the receive complete interrupt routine to be executed, provided that global interrupts are enabled. bit 6 ? txcie: tx complete interrupt enable when this bit is set (one), a setting of the txc bit in ucsra will cause the transmit complete interrupt routine to be executed, provided that global interrupts are enabled. bit 5 ? udrie: uart data register empty interrupt enable when this bit is set (one), a setting of t he udre bit in ucsra will cause the uart data register empty interrupt routine to be executed, provided that global interrupts are enabled. bit 4 ? rxen: receiver enable this bit enables the uart receiver when set (one). when the receiver is disabled, the rxc, or, and fe status flags cannot become set. if these flags are set, turning off rxen does not cause them to be cleared. bit 76543210 $0a ($2a) rxcie txcie udrie rxen txen chr9 rxb8 txb8 ucsrb read/write r/w r/w r/w r/w r/w r/w r w initial value00000010 59 at90s/ls4433 1042h?avr?04/03 bit 3 ? txen: transmitter enable this bit enables the uart transmitter when se t (one). when disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any follo wing character in udr has be en completely transmitted. bit 2 ? chr9: 9-bit characters when this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. the ninth bit is read and written by using the rxb8 and txb8 bits in ucsrb, respectively. the ninth data bit can be used as an extra stop bit or a parity bit. bit 1 ? rxb8: receive data bit 8 when chr9 is set (one), rxb8 is the ninth data bit of the received character. bit 0 ? txb8: transmit data bit 8 when chr9 is set (one), txb8 is the ninth da ta bit in the character to be transmitted. baud rate generator the baud rate generator is a frequency divider, which generates baud rates according to the following equation: baud = baud rate f ck = crystal clock frequency ubr = contents of the ubrrhi and ubrr registers, (0 - 4095) for standard crystal frequencies, the most commonly used baud rates can be generated by using the ubr settings in table 19. ubr val ues that yield an actual baud rate differ- ing less than 2% from the target baud rate are boldface in the table. however, using baud rates that have more than 1% error is not recommended. high error ratings give less noise resistance. baud f ck 16(ubr 1 ) + --------------------------------- - = 60 at90s/ls4433 1042h?avr?04/03 table 19. ubr settings at various crystal frequencies baud rate 1mhz %error 1.8432 mhz %error 2mhz %error 2.4576 mhz %error 2400 ubr= 25 0.2 ubr= 47 0.0 ubr= 51 0.2 ubr= 63 0.0 4800 ubr= 12 0.2 ubr= 23 0.0 ubr= 25 0.2 ubr= 31 0.0 9600 ubr= 6 7.5 ubr= 11 0.0 ubr= 12 0.2 ubr= 15 0.0 14400 ubr= 3 7.8 ubr= 70.0 ubr= 8 3.7 ubr= 10 3.1 19200 ubr= 2 7.8 ubr= 50.0 ubr= 6 7.5 ubr= 70.0 28800 ubr= 1 7.8 ubr= 30.0 ubr= 3 7.8 ubr= 4 6.3 38400 ubr= 1 22.9 ubr= 20.0 ubr= 2 7.8 ubr= 30.0 57600 ubr= 0 7.8 ubr= 10.0 ubr= 1 7.8 ubr= 2 12.5 76800 ubr= 0 22.9 ubr= 1 33.3 ubr= 1 22.9 ubr= 10.0 115200 ubr= 0 84.3 ubr= 00.0 ubr= 0 7.8 ubr= 0 25.0 baud rate 3.2768 mhz %error 3.6864 mhz %error 4mhz %error 4.608 mhz %error 2400 ubr= 84 0.4 ubr= 95 0.0 ubr= 103 0.2 ubr= 119 0.0 4800 ubr= 42 0.8 ubr= 47 0.0 ubr= 51 0.2 ubr= 59 0.0 9600 ubr= 20 1.6 ubr= 23 0.0 ubr= 25 0.2 ubr= 29 0.0 14400 ubr= 13 1.6 ubr= 15 0.0 ubr= 16 2.1 ubr= 19 0.0 19200 ubr= 10 3.1 ubr= 11 0.0 ubr= 12 0.2 ubr= 14 0.0 28800 ubr= 61.6 ubr= 70.0 ubr= 8 3.7 ubr= 90.0 38400 ubr= 4 6.3 ubr= 50.0 ubr= 6 7.5 ubr= 7 6.7 57600 ubr= 3 12.5 ubr= 30.0 ubr= 3 7.8 ubr= 40.0 76800 ubr= 2 12.5 ubr= 20.0 ubr= 2 7.8 ubr= 3 6.7 115200 ubr= 1 12.5 ubr= 10.0 ubr= 1 7.8 ubr= 2 20.0 baud rate 7.3728 mhz %error 8mhz %error 9.216 mhz %error 11.059 mhz %error 2400 ubr= 191 0.0 ubr= 207 0.2 ubr= 239 0.0 ubr= 287 - 4800 ubr= 95 0.0 ubr= 103 0.2 ubr= 119 0.0 ubr= 143 0.0 9600 ubr= 47 0.0 ubr= 51 0.2 ubr= 59 0.0 ubr= 71 0.0 14400 ubr= 31 0.0 ubr= 34 0.8 ubr= 39 0.0 ubr= 47 0.0 19200 ubr= 23 0.0 ubr= 25 0.2 ubr= 29 0.0 ubr= 35 0.0 28800 ubr= 15 0.0 ubr= 16 2.1 ubr= 19 0.0 ubr= 23 0.0 38400 ubr= 11 0.0 ubr= 12 0.2 ubr= 14 0.0 ubr= 17 0.0 57600 ubr= 70.0 ubr= 8 3.7 ubr= 90.0 ubr= 11 0.0 76800 ubr= 50.0 ubr= 6 7.5 ubr= 7 6.7 ubr= 80.0 115200 ubr= 30.0 ubr= 3 7.8 ubr= 40.0 ubr= 50.0 61 at90s/ls4433 1042h?avr?04/03 uart baud rate register ? ubrr this is a 12-bit register that contains the uart baud rate according to the equation on the previous page. the ubrrhi contains the four most significant bits, and the ubrr contains the eight least significant bits of the uart baud rate. bit 151413121110 9 8 $03 ($23) ????msb lsb ubrrhi $09 ($29) msb lsb ubrr 76543210 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 62 at90s/ls4433 1042h?avr?04/03 analog comparator the analog comparator compares the input values on the positive input pd6 (ain0) and negative input pd7 (ain1). when the voltage on the positive input pd6 (ain0) is higher than the voltage on the negative input pd7 (ain1), the analog comparator out- put, aco, is set (one). the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on compar- ator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 43 . figure 43. analog comparator block diagram analog comparator control and status register ? acsr bit 7 ? acd: analog comparator disable when this bit is set (one), the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog comparator. when changing the acd bit, the analog comparator interrupt must be di sabled by clearing the acie bit in acsr. otherwise, an interrupt can occur when the bit is changed. bit 6 ? ainbg: analog comparator bandgap select when this bit is set, bod is enabled and the boden is programmed, a fixed bandgap voltage of 1.22v 0.1v replaces the normal input to the positive input (ain0) of the comparator. when this bit is cleared, the normal input pin, pd6, is applied to the positive input of the comparator. bit 5 ? aco: analog comparator output aco is directly connected to the comparator output. bit 76543210 $08 ($28) acd ainbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 63 at90s/ls4433 1042h?avr?04/03 bit 4 ? aci: analog comparator interrupt flag this bit is set (one) when a comparator output event triggers the interrupt mode defined by aci1 and aci0. the analog comparator in terrupt routine is executed if the acie bit is set (one) and the i-bit in sreg is set (one ). aci is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logical ?1? to the flag. bit 3 ? acie: analog comparator interrupt enable when the acie bit is set (one) and the i-bit in the status register is set (one), the ana- log comparator interrupt is activated. when cleared (zero), the interrupt is disabled. bit 2 ? acic: analog comparator input capture enable when set (one), this bit enables the input capture function in timer/counter1 to be trig- gered by the analog comparator. the comparator output is, in this case, directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when cleared (zero), no connection between the analog comparator and the input capture function is given. to make the comparator trigger the timer/counter1 input capture interrupt, the ticie1 bit in the timer interrupt mask register (timsk) must be set (one). bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events trigger the analog comparator interrupt. the different settings are shown in table 20. note: 1. when changing the acis1/acis0 bits, the analog comparator interrupt must be dis- abled by clearing its interrupt enable bit in the acsr register. otherwise, an interrupt can occur when the bits are changed. caution: using the sbi or cbi instruction on bits other than aci in th is register will write a one back into aci if it is read as set, thus clearing the flag. table 20. acis1/acis0 settings (1) acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. 64 at90s/ls4433 1042h?avr?04/03 analog-to-digital converter features 10-bit resolution 2 lsb absolute accuracy 0.5 lsb integral non-linearity 65 - 260 s conversion time up to 15 ksps six multiplexed input channels rail-to-rail input range free run or single conversion mode interrupt on adc co nversion complete sleep mode noise canceler the at90s4433 features a 10-bit successive approximation adc. the adc is con- nected to a 6-channel analog multiplexer, which allows each pin of port c to be used as an input for the adc. the adc contains a sample and hold amplifier, which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 44. the adc has two separate analog supply voltage pins: avcc and agnd. agnd must be connected to gnd, and the voltage on avcc must not differ from v cc more than 0.3v. see the section ?adc noise canceli ng techniques? on page 70 for how to con- nect these pins. an external reference voltage must be applied to the aref pin. this voltage must be in the range 2.0 - avcc. figure 44. analog-to-digital converter block schematic adc conversion complete irq 8-bit data bus 90 adc multiplexer select (admux) adc ctrl & status register (adcsr) adc data register (adch/adcl) mux2 adie adie adfr adsc aden adif adif mux1 mux0 adps0 adps1 adps2 6- channel mux conversion logic 10-bit dac + - sample & hold comparator analog inputs external reference voltage 65 at90s/ls4433 1042h?avr?04/03 operation the adc can operate in two modes: single conversion and free run mode. in single conversion mode, each conversion will have to be initiated by the user. in free run mode, the adc is constantly sampling and updating the adc data register. the adfr bit in adcsr selects between the two available modes. the admux register selects which one of the six analog input channels is to be used as input to the adc. the adc is enabled by writing a logical ?1? to the adc enable bit, aden in adcsr. the first conversion that is started after enabling the adc will be preceded by a dummy conversion to initialize the a dc. to the user, the only diffe rence will be that this conver- sion takes 12 clock cycles more than a normal conversion. a conversion is started by writing a logical ?1? to the adc start conversion bit, adsc. this bit will stay high as long as the conversion is in progress and be se t to zero by hard- ware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conversion before performing the channel change. as the adc generates a 10-bit result, two data registers, adch and adcl, must be read to get the result when the conversion is complete. special data protection logic is used to ensure that the contents of the data registers belong to the same result when they are read. this mechanism works as follows: when reading data, adcl must be read first. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read and a conversion completes before adch is read, none of the registers are updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt, adif, which can be triggered when a conversion com- pletes. when adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result gets lost. prescaling figure 45. adc prescaler the adc contains a prescaler, which divides the system clock to an acceptable adc clock frequency. the adc accepts input clock frequencies in the range 50 - 200 khz. applying a higher input freq uency will result in a poorer accuracy (see ?adc character- istics? on page 71). the adps0 - adps2 bits in adcsr are used to generate a proper adc clock input fre- quency from any xtal frequency above 100 khz. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsr. the prescaler 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden 66 at90s/ls4433 1042h?avr?04/03 keeps running for as long as the aden bit is set and is continuously reset when aden is low. when initiating a conversion by setting the ad sc bit in adcsr, the conversion starts at the following rising edge of the adc cloc k cycle. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of the conversion. the result is ready and writ- ten to the adc result register after 13 cycles. in single conv ersion mode, the adc needs one more clock cycle before a new conversion can be started (see figure 47). if adsc is set high in this period, the adc wi ll start the new conversion immediately. in free run mode, a new conversion will be started immediately after the result is written to the adc result register. using free run mode and an adc clock frequency of 200 khz gives the lowest conversion time, 65 s, equivalent to 15.4 ksps. for a summary of conversion times, see table 21. figure 46. adc timing diagram, first conversion (single conversion mode) msb of result lsb of result adc clock adsc hold strobe adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 dummy conversion actual conversion second conversion table 21. adc conversion time condition sample cycle number result ready(cycle number) total conversion time (cycles) total conversion time (s) 1st conversion, free run 13.5 25 25 125 - 500 1st conversion, single 13.5 25 26 130 - 520 free run conversion 1.5 13 13 65 - 260 single conversion 1.5 13 14 70 - 280 67 at90s/ls4433 1042h?avr?04/03 figure 47. adc timing diagram, single conversion figure 48. adc timing diagram, free run conversion adc noise canceler function the adc features a noise canceler that enab les conversion during idle mode to reduce noise induced from the cpu core. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy converting. single conver- sion mode must be selected and the adc conversion complete interrupt must be enabled. thus: aden = 1 adsc = 0 adfr = 0 adie = 1 2. enter idle mode. the adc will start a conversion once the cpu has been halted. 3. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the mcu and execute th e adc conversion complete interrupt routine. 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 11 12 13 msb of result lsb of result adc clock adsc hold strobe adif adch adcl cycle number 12 one conversion next conversion 68 at90s/ls4433 1042h?avr?04/03 adc multiplexer select register ? admux bit 7 ? res: reserved bit this bit is a reserved bit in the at90s4433, and should be written to zero if accessed. bit 6 ? adcbg: adc bandgap select when this bit is set and the bod is enabled (boden fuse is programmed), a fixed bandgap voltage of 1.22v 0.1v replaces the normal input to the adc. when this bit is cleared, the normal input pin (as selected by mux2..mux0) is applied to the adc. bits 5..3 ? res: reserved bits these bits are reserved bits in the at90s4433, and should be written to zero if accessed. bits 2..0 ? mux2..mux0: analog channel select bits 2 - 0 the value of these three bits selects which analog input 5 - 0 is connected to the adc. adc control and status register ? adcsr ? bit 7 ? aden: adc enable writing a logical ?1? to this bit enables the ad c. by clearing this bit to zero, the adc is turned off. turning the adc of f while a conversion is in progress will terminate this conversion. bit 6 ? adsc: adc start conversion in single conversion mode, a logical ?1? must be written to this bit to start each conver- sion. in free run mode, a logical ?1? must be written to this bit to start the first conversion. the first time adsc has been wr itten after the adc has been enabled, or if adsc is written at the same time as t he adc is enabled, a dummy conversion will pre- cede the initiated conversion. this dummy co nversion performs init ialization of the adc. adsc remains high during the conversion. ad sc goes low after the conversion is com- plete, but before the result is written to the adc data registers. this allows a new conversion to be initiated before the current conversion is complete. the new conver- sion will then start immediately after the current conversion completes. when a dummy conversion precedes a real conversion, adsc will stay high until the real conversion completes. writing a ?0? to this bit has no effect. bit 76543210 $07 ($27) ? adcbg ? ? ? mux2 mux1 mux0 admux read/write r r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $06 ($26) aden adsc adfr adif adie adps2 adps1 adps0 adcsr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 69 at90s/ls4433 1042h?avr?04/03 bit 5 ? adfr: adc free run select when this bit is set (one), the adc operates in free run mode. in this mode, the adc samples and updates the data registers contin uously. clearing this bit (zero) will termi- nate free run mode. bit 4 ? adif: adc interrupt flag this bit is set (one) when an adc conversion completes and the data registers are updated. the adc conversion complete interr upt is executed if the adie bit and the i- bit in sreg are set (one). adif is clea red by hardware when executing the correspond- ing interrupt handling vector. alte rnatively, adif is cleared by writing a logical ?1? to the flag. beware that if doing a read-modify-write on adcsr, a pending interrupt can be disabled. this also applies if the sbi and cbi instructions are used. bit 3 ? adie: adc interrupt enable when this bit is set (one) and the i-bit in sreg is set (one), the adc conversion com- plete interrupt is activated. bits 2..0 ? adps2..adps0: adc prescaler select bits these bits determine the division factor between the xtal frequency and the input clock to the adc. adc data register ? adcl and adch when an adc conversion is complete, the result is found in these two registers. in free run mode, it is essential that both registers are read and that adcl is read before adch. table 22. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 bit 151413121110 9 8 $05 ($25) ??????adc9 adc8 adch $04 ($26) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 70 at90s/ls4433 1042h?avr?04/03 scanning multiple channels since change of analog channel always is delayed until a conversion is finished, the free run mode can be used to scan multiple channels without interrupting the con- verter. typically, the adc conversion complete interrupt will be used to perform the channel shift. however, the user should take the following fact into consideration: the interrupt triggers once the result is ready to be read. in free run mode, the next conver- sion will start immediately when the interr upt triggers. if admux is changed after the interrupt triggers, the next conversion has already started and the old setting is used. adc noise canceling techniques digital circuitry inside and outside the at90s4433 generates emi, which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. the analog part of the at90s4433 and all analog components in the application should have a separate analog ground plane on the pcb. this ground plane is connected to the digital ground plane via a single point on the pcb. 2. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane and keep them well away from high-speed switching digital tracks. 3. the avcc pin on the at90s4433 should be connected to the digital v cc supply voltage via an lc network as shown in figure 49. 4. use the adc noise canceler function to reduce induced noise from the cpu. 5. if some port c pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. figure 49. adc power connections note that since avcc feeds the port c output drivers, the rc network shown should not be employed if any port c serve as outputs. 28 27 26 25 24 23 22 21 20 19 pc5 (adc5) pc4 (adc4) pc3 (adc3) pc2 (adc2) pc1 (adc1) pc0 (adc0) agnd aref avcc pb5 vcc 100 nf analog ground plane at90s4433 10 h 71 at90s/ls4433 1042h?avr?04/03 notes: 1. minimum for avcc is 2.7v. 2. maximum for avcc is 6.0v. adc characteristics t a = -40 c to 85 c symbol parameter condition min typ max units resolution 10 bits absolute accuracy v ref = 4v adc clock = 200 khz 12lsb absolute accuracy v ref = 4v adc clock = 1 mhz 4lsb absolute accuracy v ref = 4v adc clock = 2 mhz 16 lsb integral non-linearity v ref > 2v 0.5 lsb differential non-linearity v ref > 2v 0.5 lsb zero error (offset) 1 lsb conversion time 65 260 s clock frequency 50 200 khz avcc analog supply voltage v cc - 0.3 (1) v cc + 0.3 (2) v v ref reference voltage 2 avcc v r ref reference input resistance 6 10 13 k ? r ain analog input resistance 100 m ? 72 at90s/ls4433 1042h?avr?04/03 i/o ports all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the sbi and cbi instructions. the same applies for changing drive value (if co nfigured as output) or enabling/disabling of pull-up resistors (if configured as input). port b port b is a 6-bit bi-directional i/o port. three i/o memory address locations are allocated for the port b, one each for the data register ? portb, $18($38), data direction register ? ddrb, $17($37), and the port b input pins ? pinb, $16($36). the port b input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port b output buffers can sink 20 ma and thus drive led displays di rectly. when pins pb0 to pb7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resis- tors are activated. the port b pins with alternate functions are shown in table 23. when the pins are used for the alternate function, the ddrb and portb registers have to be set according to the alternate function description. port b data register ? portb port b data direction register ? ddrb port b input pins address ? pinb table 23. port b pin alternate functions port pin alternate functions pb0 icp (timer/counter1 input capture pin) pb1 oc1 (timer/counter1 output compare match output) pb2 ss (spi slave select input) pb3 mosi (spi bus master output/slave input) pb4 miso (spi bus master input/slave output) pb5 sck (spi bus serial clock) bit 76543210 $18 ($38) ? ? portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $17 ($37) ? ? ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $16 ($36) ? ? pinb5 pinb4 pinb3 pi nb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value 0 0 n/a n/a n/a n/a n/a n/a 73 at90s/ls4433 1042h?avr?04/03 the port b input pins address (pinb) is not a register; this address enables access to the physical value on each port b pin. when reading portb, the port b data latch is read, and when reading pinb, the logical values present on the pins are read. port b as general digital i/o all six pins in port b have equal functi onality when used as digital i/o pins. pbn, general i/o pin: the ddbn bit in the ddrb register selects the direction of this pin. if ddbn is set (one), pbn is configured as an output pin. if ddbn is cleared (zero), pbn is configured as an input pin. if portbn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the portbn has to be cleared (zero) or the pin has to be configured as an output pin. the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. note: 1. n: 5..0, pin number. alternate functions of port b the alternate pin configuration is as follows: sck ? port b, bit 5 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input, regardless of the setting of ddb5. when the spi is enabled as a master, the da ta direction of this pin is controlled by ddb5. when the pin is forced to be an input, the pull-up can still be controlled by the portb5 bit. see the description of the spi port for further details. miso ? port b, bit 4 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input, regardless of the setting of ddb4. when the spi is enabled as a slave, th e data direction of this pin is controlled by ddb4. when the pin is forced to be an input, the pull-up can still be controlled by the portb4 bit. see the description of the spi port for further details. mosi ? port b, bit 3 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input, regardless of the setting of ddb3. when the spi is enabled as a master, the da ta direction of this pin is controlled by ddb3. when the pin is forced to be an input, the pull-up can still be controlled by the portb3 bit. see the description of the spi port for further details. ss ? port b, bit 2 ss : slave port select input. when the spi is enabled as a slave, this pin is configured as an input, regardless of the setting of ddb2. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is table 24. ddbn effects on port b pins (1) ddbn portbn i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input yes pbn will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output 74 at90s/ls4433 1042h?avr?04/03 controlled by ddb2. when the pin is forced to be an input, the pull-up can still be con- trolled by the portb2 bit. see the description of the spi port for further details. oc1 ? port b, bit 1 oc1, output compare match output: pb1 pin can serve as an external output for the timer/counter1 output compare. the pin has to be configured as an output (ddb1 set [one]) to serve this function. see the timer description on how to enable this function. the oc1 pin is also the output pi n for the pwm mode timer function. icp ? port b, bit 0 icp, input capture pin: pb0 pin can serve as an external input for the timer/counter1 input capture. the pin has to be configured as an input (ddb0 cleared [zero]) to serve this function. see the timer description on how to enable this function. figure 50. port b schematic diagram (pin pb0) data bus d d q q reset reset c c wd wp rd mos pull- up pb0 r r wp: wd: rl: rp: rd: acic: aco: write portb write ddrb read portb latch read portb pin read ddrb comparator ic enable comparator output ddb6 portb0 noise canceler edge select icf1 icnc1 ices1 0 1 acic aco rl rp 75 at90s/ls4433 1042h?avr?04/03 figure 51. port b schematic diagram (pin pb1) figure 52. port b schematic diagram (pin pb2) pb1 ddb1 portb1 wp: wd: rl: rp: rd: write portb write ddrb read portb latch read portb pin read ddrb data bus d d q q reset reset c c wd wp rd mos pull- up pb2 spi ss mstr spe wp: wd: rl: rp: rd: mstr: spe: write portb write ddrb read portb latch read portb pin read ddrb spi master enable spi enable ddb2 portb2 rl rp 76 at90s/ls4433 1042h?avr?04/03 figure 53. port b schematic diagram (pin pb3) figure 54. port b schematic diagram (pin pb4) data bus d d q q reset reset c c wd wp rd mos pull- up pb3 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb3 portb3 spe mstr spi master out spi slave in rl rp data bus d d q q reset reset c c wd wp rd mos pull- up pb4 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb4 portb4 spe mstr spi slave out spi master in rl rp 77 at90s/ls4433 1042h?avr?04/03 figure 55. port b schematic diagram (pin pb5) port c port c is a 6-bit bi-directional i/o port. three i/o memory address locations are allocated for the port c, one each for the data register ? portc, $15($35), data direction register ? ddrc, $14($34), and the port c input pins ? pinc, $13($33). the port c input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port c output buffers can sink 20 ma and thus drive led displays di rectly. when pins pc0 to pc5 are used as inputs and are externally pulled low, they will source current if the internal pull-up resis- tors are activated. port c has an alternate function as analog inputs for the adc. if some port c pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. this might corrupt the result of the conversion. during power-down mode, the schmitt triggers of the digital inputs are disconnected. this allows an analog voltage close to v cc /2 to be present during power-down without causing excessive power consumption. data bus d d q q reset reset c c wd wp rd mos pull- up pb5 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb5 portb5 spe mstr spi clock out spi clock in rl rp 78 at90s/ls4433 1042h?avr?04/03 port c data register ? portc port c data direction register ? ddrc port c input pins address ? pinc the port c input pins address (pinc) is not a register; this address enables access to the physical value on each port c pin. when reading portc, the port c data latch is read, and when reading pinc, the logical values present on the pins are read. port c as general digital i/o all six pins in port c have equal functionality when used as digital i/o pins. pcn, general i/o pin: the ddcn bit in the dd rc register selects the direction of this pin. if ddcn is set (one), pcn is configured as an output pin. if ddcn is cleared (zero), pcn is configured as an input pin. if portcn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, portcn has to be cleared (zero) or the pin has to be configured as an output pin.the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. note: 1. n: 5..0, pin number bit 76543210 $15 ($35) ? ? portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $14 ($34) ? ? ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $13 ($33) ? ? pinc5 pinc4 pinc3 pi nc2 pinc1 pinc0 pinc read/writerrrrrrrr initial value 0 0 n/a n/a n/a n/a n/a n/a table 25. ddcn effects on port c pins (1) ddcn portcn i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input yes pcn will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output 79 at90s/ls4433 1042h?avr?04/03 port c schematics note that all port pins are synchronized. the synchronization latch is, however, not shown in the figure. figure 56. port c schematic diagrams (pins pc0 - pc5) data bus d d q q reset reset c c wd wp rd mos pull- up pcn adcn to adc mux wp: wd: rl: rp: rd: n: write portc write ddrc read portc latch read portc pin read ddrc 0 - 5 ddcn portcn rl rp pwrdn pwrdn: power down mode 80 at90s/ls4433 1042h?avr?04/03 port d port d is an 8-bit bi-directional i/o port with internal pull-up resistors. three i/o memory address locations are allocated for port d, one each for the data register ? portd, $12($32), data direction register ? ddrd, $11($31), and the port d input pins ? pind, $10($30). the port d input pins address is read only, while the data register and the data direction register are read/write. the port d output buffers can sink 20 ma. as inputs, port d pins that are externally pulled low will source current if t he pull-up resistor s are activated. some port d pins have alternate functions as shown in table 26. port d data register ? portd port d data direction register ? ddrd port d input pins address ? pind the port d input pins address (pind) is not a register; this address enables access to the physical value on each port d pin. when reading portd, the port d data latch is read, and when reading pind, the logical values present on the pins are read. table 26. port d pin alternate functions port pin alternate function pd0 rxd (uart input line) pd1 txd (uart output line) pd2 int0 (external interrupt 0 input) pd3 int1 (external interrupt 1 input) pd4 t0 (timer/counter 0 external counter input) pd5 t1 (timer/counter 1 external counter input) pd6 ain0 (analog comparator positive input) pd7 ain1 (analog comparator negative input) bit 76543210 $12 ($32) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $11 ($31) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $10 ($30) pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 81 at90s/ls4433 1042h?avr?04/03 port d as general digital i/o pdn, general i/o pin: the dddn bit in the ddrd register se lects the direction of this pin. if dddn is set (one), pdn is configured as an output pin. if dddn is cleared (zero), pdn is configured as an input pin. if pdn is set (one) when configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the pdn has to be cleared (zero) or the pin has to be configured as an output pin.the port pins are tri- stated when a reset condition becomes active, even if the clock is not running. note: 1. n: 7,6..0, pin number. alternate functions of port d ain1 ? port d, bit 7 ain1, analog comparator negative input. when configured as an input (ddd7 is cleared [zero]), and with the internal mos pull-up resistor switched off (pd7 is cleared [zero]), this pin also serves as the negat ive input of the on-chip analog comparator. during power-down mode, the schmitt trigger of the digital input is disconnected. this allows analog signals, which are close to v cc /2, to be present during power-down with- out causing excessive power consumption. ain0 ? port d, bit 6 ain0, analog comparator positive input. when configured as an input (ddd6 is cleared [zero]), and with the internal mos pull-up resi stor switched off (pd6 is cleared [zero]), this pin also serves as the positive input of the on-chip analog comparator. during power-down mode, the schmitt trigger of the digital input is disconnected. this allows analog signals, which are close to v cc /2, to be present during power-down without causing excessive power consumption. t1 ? port d, bit 5 t1, timer/counter1 counter source. see the timer description for further details t0 ? port d, bit 4 t0: timer/counter0 counter source. see the timer description for further details. int1 ? port d, bit 3 int1, external interrupt source 1: the pd3 pin can serve as an external interrupt source to the mcu. see the interrupt description for further details and how to enable the source. int0 ? port d, bit 2 int0, external interrupt source 0: the pd2 pin can serve as an external interrupt source to the mcu. see the interrupt description for further details and how to enable the source. table 27. dddn bits on port d pins (1) dddn portdn i/o pull-up comment 0 0 input no tri-state (high-z) 0 1 input yes pdn will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output 82 at90s/ls4433 1042h?avr?04/03 txd ? port d, bit 1 transmit data (data output pin for the uart). when the uart transmitter is enabled, this pin is configured as an output, regardless of the value of ddd1. rxd ? port d, bit 0 receive data (data input pin for the uart). when the uart receiver is enabled, this pin is configured as an input, regardless of the value of ddd0. when the uart forces this pin to be an input, a logical ?1? in portd0 will turn on the internal pull-up. port d schematics note that all port pins are synchronized. the synchronization latches are, however, not shown in the figures. figure 57. port d schematic diagram (pin pd0) data bus d d q q reset reset c c wd wp rd mos pull- up pd0 rxd rxen wp: wd: rl: rp: rd: rxd: rxen: write portd write ddrd read portd latch read portd pin read ddrd uart receive data uart receive enable ddd0 portd0 rl rp 83 at90s/ls4433 1042h?avr?04/03 figure 58. port d schematic diagram (pin pd1) figure 59. port d schematic diagram (pins pd2 and pd3) data bus d d q q reset reset c c wd wp rd rp rl mos pull- up pd1 r r wp: wd: rl: rp: rd: txd: txen: write portd write ddrd read portd latch read portd pin read ddrd uart transmit data uart transmit enable ddd1 portd1 txen txd 84 at90s/ls4433 1042h?avr?04/03 figure 60. port d schematic diagram (pins pd4 and pd5) figure 61. port d schematic diagram (pins pd6 and pd7) wp: wd: rl: rp: rd: n: write portd write ddrd read portd latch read portd pin read ddrd 4, 5 pdn portbn dddn 2 data bus d d q q reset reset c c wd wp rd mos pull- up pdn ainm to comparator wp: wd: rl: rp: rd: n: m: write portd write ddrd read portd latch read portd pin read ddrd 6, 7 0, 1 pwrdn dddn portdn rl rp pwrdn: power down mode 85 at90s/ls4433 1042h?avr?04/03 memory programming program and data memory lock bits the at90s4433 mcu provides two lock bits, which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 28. the lock bits can only be erased with the chip erase command. note: 1. in parallel mode, programming of the fuse bits are also disabled. program the fuse bits before programming the lock bits. fuse bits the at90s4433 has six fu se bits, spien, bodlevel, boden and cksel2..0. when the spien fuse is programmed (?0?), serial program and data downloading is enabled. default value is programmed (?0? ). this bit is not accessible in serial programming mode. the bodlevel fuse selects the brown-out detection level and changes the start- up times. see ?brown-out detection? on page 25. default value is unprogrammed (?1?). when the boden fuse is programmed (?0?), the brown-out detector is enabled. see ?brown-out detection? on page 25. default value is unprogrammed (?1?). cksel2..0: see table 5 on page 23 for which combination of cksel2..0 to use. default value is ?010?. signature bytes all atmel microcontrollers have a 3-byte signature code that identifies the device. this code can be read in both serial and parallel mode. the three bytes reside in a separate address space. for the at90s4433 (1) they are: 1. $000: $1e (indicates manufactured by atmel) 2. $001: $92 (indicates 4 kb flash memory) 3. $002: $03 (indicates at90s4433 device when signature byte $001 is $92) note: 1. when both lock bits are programmed ( lock mode 3), the signature bytes cannot be read in serial mode. reading the signature bytes will return $00, $01 and $02. table 28. lock bit protection modes memory lock bits protection type mode lb1 lb2 1 1 1 no memory lock features enabled. 2 0 1 further programming of the flash and eeprom is disabled. (1) 3 0 0 same as mode 2, and verify is also disabled. 86 at90s/ls4433 1042h?avr?04/03 programming the flash and eeprom atmel?s at90s4433 offers 4k bytes of in-system reprogrammable flash program memory and 256 bytes of eeprom data memory. the at90s4433 is shipped with the on-c hip flash program and eeprom data mem- ory arrays in the erased state (i.e., contents = $ff) and ready to be programmed. this device supports a high-voltage (12v) parallel programming mode and a low-voltage serial programming mode. the +12v is used for programming enable only, and no cur- rent of significance is drawn by this pi n. the serial programming mode provides a convenient way to download program and data into the at90s4433 inside the user?s system. the program and data memory arrays on the at90s4433 are programmed byte-by- byte in either programming mode. for the eeprom, an auto-erase cycle is provided within the self-timed write in struction in the serial programming mode. during program- ming, the supply voltage must be in accordance with table 29. parallel programming this section describes how to parallel program and verify flash program memory, eeprom data memory, lock bits an d fuse bits in the at90s4433. signal names in this section, some pins of the at90s44 33 are referenced by si gnal names describing their function during parallel programmi ng. see figure 62 and table 30. pins not described in table 30 are referenced by pin name. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a posi- tive pulse. the bit codings are shown in table 31. when pulsing wr or oe , the command loaded determines the action executed. the command is a byte where the different bits are assigned functions as shown in table 32. figure 62. parallel programming table 29. supply voltage during programming part serial programming parallel programming at90ls4433 2.7 - 6.0v 4.5 - 5.5v at90s4433 4.0 - 6.0v 4.5 - 5.5v at90s4433 vcc +5v reset gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 +12v rdy/bsy oe bs xa0 xa1 wr pc1 - pc0, pb5 - pb0 data 87 at90s/ls4433 1042h?avr?04/03 enter programming mode the following algorithm puts the devi ce in parallel programming mode: 1. apply supply voltage according to table 29, between v cc and gnd. 2. set the reset and bs pin to ?0? and wait at least 100 ns. 3. apply 11.5 - 12.5v to reset . any activity on bs within 100 ns after +12v has been applied to reset will cause the device to fa il entering programming mode. table 30. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs pd4 i byte select (?0? selects low byte, ?1? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 data pc1 - 0, pb5 - 0 i/o bi-directional data bus (output when oe is low) table 31. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs) 0 1 load data (high or low data byte for flash determined by bs) 1 0 load command 1 1 no action, idle table 32. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 88 at90s/ls4433 1042h?avr?04/03 chip erase the chip erase command will erase the flash and eeprom memories and the lock bits. the lock bits are not reset until the flash and eeprom have been completely erased. the fuse bits are not changed. chip erase must be performed before the flash or eeprom is reprogrammed. a: load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a t wlwh_ce wide negative pulse to execute chip erase. see table 33 for t wlwh_ce value. chip erase does not generate any activity on the rdy/bsy pin. programming the flash a: load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b: load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs to ?1?. this selects high byte. 3. set data = address high byte ($00 - $07). 4. give xtal1 a positive pulse. this loads the address high byte. c: load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs to ?0?. this selects low byte. 3. set data = address low byte ($00 - $ff). 4. give xtal1 a positive pulse. this loads the address low byte. d: load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte ($00 - $ff). 3. give xtal1 a positive pulse. this loads the data low byte. e: write data low byte 1. set bs to ?0?. this selects low data. 2. give wr a negative pulse. this starts programming of the data byte. rdy/bsy goes low. 3. wait until rdy/bsy goes high to program the next byte. (see figure 63 for signal waveforms.) f: load data high byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data high byte ($00 - $ff). 3. give xtal1 a positive pulse. this loads the data high byte. 89 at90s/ls4433 1042h?avr?04/03 g: write data high byte 1. set bs to ?1?. this selects high data. 2. give wr a negative pulse. this starts programming of the data byte. rdy/bsy goes low. 3. wait until rdy/bsy goes high to program the next byte. (see figure 64 for signal waveforms.) the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered: the command needs to be loaded only once when writing or reading multiple memory locations. address high byte needs to be loaded only before programming a new 256-word page in the flash. skip writing the data value $ff, that is, the contents of the entire flash and eeprom after a chip erase. these considerations also apply to eeprom programming and flash, eeprom and signature bytes reading. figure 63. programming the flash waveforms $10 addr. high addr. low data low data xa1 xa0 bs xtal1 wr rdy/bsy reset oe 12v 90 at90s/ls4433 1042h?avr?04/03 figure 64. programming the flash waveforms (continued) reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? for details on command and address loading): a: load command ?0000 0010?. b: load address high byte ($00 - $07). c: load address low byte ($00 - $ff). 1. set oe to ?0?, and bs to ?0?. the flash word low byte can now be read at data. 2. set bs to ?1?. the flash word high byte can now be read from data. 3. set oe to ?1?. programming the eeprom the programming algorithm for the eeprom data memory is as follows (refer to ?pro- gramming the flash? for details on command, address and data loading): a: load command ?0001 0001?. b: load address low byte ($00 - $ff). c: load data low byte ($00 - $ff). d: write data low byte. reading the eeprom the algorithm for readi ng the eeprom memory is as follows (refer to ?programming the flash? for details on command and address loading): a: load command ?0000 0011?. b: load address low byte ($00 - $ff). 1. set oe to ?0?, and bs to ?0?. the eeprom data byte can now be read at data. 2. set oe to ?1?. data high data xa1 xa0 bs xtal1 wr rdy/bsy reset +12v oe 91 at90s/ls4433 1042h?avr?04/03 programming the fuse bits the algorithm for programming the fuse bits is as follows (refer to ?programming the flash? for details on command and data loading): a: load command ?0100 0000?. b: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. bit 5 = spien fuse bit bit 4 = bodlevel fuse bit bit 3 = boden fuse bit bit 2 = cksel2 fuse bit bit 1 = cksel1 fuse bit bit 0 = cksel0 fuse bit bits 7 - 6 = ?1?. these bits are reserved and should be left unprogrammed (?1?). 1. give wr a t wlwh_pfb wide negative pulse to execute the programming, t wlwh_pfb is found in table 33. programming the fuse bits does not generate any activity on the rdy/bsy pin. programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? for details on command and data loading): a: load command ?0010 0000?. b: load data low byte. bit n = ?0? programs the lock bit. bit 2 = lock bit 2 bit 1 = lock bit 1 bits 7 - 3, 0 = ?1?. these bits are reserved and should be left unprogrammed (?1?). c: write data low byte. the lock bits can only be cleared by executing chip erase. reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? for details on command loading): a: load command ?0000 0100?. 1. set oe to ?0?, and bs to ?0?. the status of the fuse bits can now be read at data (?0? means programmed). bit 5 = spien fuse bit bit 4 = bodlevel fuse bit bit 3 = boden fuse bit bit 2 = cksel2 fuse bit bit 1 = cksel1 fuse bit bit 0 = cksel0 fuse bit 2. set bs to ?1?. the status of the lock bits can now be read at data (?0? means programmed). bit 2 = lock bit 2 bit 1= lock bit 1 3. set oe to ?1?. 92 at90s/ls4433 1042h?avr?04/03 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? for details on command and address loading): a: load command ?0000 1000?. b: load address low byte ($00 - $02). 1. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 2. set oe to ?1?. parallel programming characteristics figure 65. parallel programming timing notes: 1. use t wlwh_ce for chip erase and t wlwh_pfb for programming the fuse bits. 2. if t wlwh is held longer than t wlrh , no rdy/bsy pulse will be seen. table 33. parallel programming characteristics t a = 25 c 10%, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250.0 a t dvxh data and control setup before xtal1 high 67.0 ns t xhxl xtal1 pulse width high 67.0 ns t xldx data and control hold after xtal1 low 67.0 ns t xlwl xtal1 low to wr low 67.0 ns t bvwl bs valid to wr low 67.0 ns t rhbx bs hold after rdy/bsy high 67.0 ns t wlwh wr pulse width low (1) 67.0 ns t whrl wr high to rdy/bsy low (2) 20.0 ns t wlrh wr low to rdy/bsy high (2) 0.5 0.7 0.9 ms t xlol xtal1 low to oe low 67.0 ns t oldv oe low to data valid 20.0 ns t ohdz oe high to data tri-stated 20.0 ns t wlwh_ce wr pulse width low for chip erase 5.0 10.0 15.0 ms t wlwh_pfb wr pulse width low for programming the fuse bits 1.0 1.5 1.8 ms data & contol (data, xa0/1, bs) data write read xtal1 t xhxl t wlwh t dvxh t xlol t oldv t whrl t wlrh wr rdy/bsy oe t xldx t xlwl t rhbx t ohdz t bvwl 93 at90s/ls4433 1042h?avr?04/03 serial downloading both the program and data memory arrays can be programmed using the spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output) (see fi gure 66). after reset is set low, the programming enable instruction needs to be executed first before program/erase instructions can be executed. figure 66. serial programming and verify for the eeprom, an auto-erase cycle is provided within the self-tim ed write instruction and there is no need to first execute the chip erase instruction. the chip erase instruc- tion turns the content of every memory location in both the program and eeprom arrays into $ff. the program and eeprom memory arrays have separate address spaces: 0000 to $07ff for program memory and $00 00 to $00ff for eeprom memory. either an external system clock is supplied at pin xtal1 or a crystal needs to be con- nected across pins xtal1 and xtal2. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 xtal1 clock cycles high: > 2 xtal1 clock cycles serial programming algorithm when writing serial data to the at90s4433, data is clocked on the rising edge of clk. when reading data from the at90s4433, data is clocked on the falling edge of clk. see figure 67, figure 68 and table 36 for details. to program and verify the at90s4433 in the serial programming mode, the following sequence is recommended (see 4-byte instruction formats in table 35 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. if a crystal is not connected across pins xtal1 and xtal2, apply a clock signal to the xtal1 pin. in some systems, the programmer cannot guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two xtal1 cycles? duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the program- ming enable serial instruction to pin mosi/pb3. 3. the serial programming instructions will not work if the communication is out of synchronization. when in sync, the seco nd byte ($53) will echo back when issu- at90s/ls4433 vcc 4.0 - 6.0 v (at90s4433) 2.7 - 6.0 v (at90ls4433) pb5(sck) pb4(miso) pb3(mosi) reset gnd xtal1 clock in gnd data out instr. in clock input 94 at90s/ls4433 1042h?avr?04/03 ing the third byte of the programming enable instruction. whether or not the echo is correct, all four bytes of the instruction must be transmitted. if the $53 did not echo back, give sck a positive pulse and issue a new programming enable instruction. if the $53 is not seen within 32 attempts, there is no functional device connected. 4. if a chip erase is performed (must be done to erase the flash), wait t wd_erase after the instruction, give reset a positive pulse, and start over from step 2. see table 37 on page 97 for t wd_erase value. 5. the flash or eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate writ e instruction. an eeprom memory location is first automatically erased before new data is written. use data polling to detect when the next by te in the flash or eeprom can be writ- ten. if polling is not used, wait t wd_prog before transmitting the next instruction. in an erased device, no $ffs in the data file(s) need to be programmed. see table 38 on page 97 for t wd_prog value. 6. any memory location can be verified by using the read instruction, which returns the content at the selected address at serial output miso/pb4. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set xtal1 to ?0? (if a crystal is not used). set reset to ?1?. tu r n v cc power off. data polling eeprom when a byte is being programmed into the eeprom, reading the address location being programmed will give the value p1 until the auto-erase is finished, and then the value p2. see table 34 for p1 and p2 values. at the time the device is ready for a new eeprom byte , the programm ed value will read correctly. this is used to de termine when the next byte ca n be written. this will not work for the values p1 and p2, so when programming th ese values, the user will have to wait for at least the prescribed time t wd_prog before programming the next byte. see table 38 for t wd_prog value. as a chip-erased device cont ains $ff in all locations, program- ming of addresses that are meant to contain $ff can be skipped. this does not apply if the eeprom is reprogra mmed without first chip erasing the device. table 34. read back value during eeprom polling part p1 p2 at90s/ls4433 $00 $ff 95 at90s/ls4433 1042h?avr?04/03 data polling flash when a byte is being programmed into the flash, reading the address location being programmed will give the value $f f. at the time the device is ready for a new byte, the programmed value will read correct ly. this is used to determ ine when the next byte can be written. this will not work for the value $ff, so when programmi ng this value, the user will have to wait for at least t wd_prog before programming the next byte. as a chip- erased device contains $ff in all locations, programming of addresses that are meant to contain $ff can be skipped. figure 67. serial programm ing waveforms msb msb lsb lsb serial clock input pb5(sck) serial data input pb3(mosi) serial data output pb4(miso) 96 at90s/ls4433 1042h?avr?04/03 note: 1. the signature bytes are not readable in lo ck mode 3, i.e., both lock bits programmed. a = address high bits b = address low bits h = 0 ? low byte, 1 ? high byte o = data out i = data in x = don?t care 1 = lock bit 1 2 = lock bit 2 3 = cksel0 fuse 4 = cksel1 fuse 5 = cksel2 fuse 6 = boden fuse 7 = bodlevel fuse 8 = spien fuse table 35. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming while reset is low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase flash and eeprom memory arrays. read program memory 0010 h 000 xxxx x aaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . write program memory 0100 h 000 xxxx x aaa bbbb bbbb iiii iiii write h (high or low) data i to program memory at word address a : b . read eeprom memory 1010 0000 xxxx xxxx bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 xxxx xxxx bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . write lock bits 1010 1100 1111 1 21 1 xxxx xxxx xxxx xxxx write lock bits. set bits 1,2 = ?0? to program lock bits. read lock bits 0101 1000 xxxx xxxx xxxx xxxx xxxx x 21 x read lock bits. ?0? = programmed, ?1? = unprogrammed. read sigature bytes 0011 0000 xxxx xxxx xxxx xx bb oooo oooo read signature byte o at address b . (1) write fuse bits 1010 1100 101 7 6543 xxxx xxxx xxxx xxxx set bits 7 - 3 = ?0? to program, ?1? to unprogram. read fuse bits 0101 0000 xxxx xxxx xxxx xxxx xx 87 6543 read fuse bits. ?0? = programmed, ?1? = unprogrammed. 97 at90s/ls4433 1042h?avr?04/03 serial programming characteristics figure 68. serial programming timing table 36. serial programming characteristics, t a = -40 c to 85 c, v cc = 2.7 - 6.0v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency (v cc = 2.7 - 6.0v) 0 4 mhz t clcl oscillator period (v cc = 2.7 - 6.0v) 250 ns 1/t clcl oscillator frequency (v cc = 4.0 - 6.0v) 0 8 mhz t clcl oscillator period (v cc = 4.0 - 6.0v) 125 ns t shsl sck pulse width high 2 t clcl ns t slsh sck pulse width low 2 t clcl ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid 10 16 32 ns table 37. minimum wait delay after th e chip erase instruction symbol 3.2v 3.6v 4.0v 5.0v t wd_erase 18 ms 14 ms 12 ms 8 ms table 38. minimum wait delay after writ ing a flash or eeprom location symbol 3.2v 3.6v 4.0v 5.0v t wd_prog 9 ms 7 ms 6 ms 4 ms mosi miso sck t ovsh t shsl t slsh t shox t sliv 98 at90s/ls4433 1042h?avr?04/03 electrical characteristics absolute maximum ratings* operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150 c voltage on any pin except reset with respect to ground .............................-1.0v to v cc + 0.5v voltage on reset with respect to ground ....-1.0v to +13.0v maximum operating voltage ............................................ 6.6v dc current per i/o pin ............................................... 40.0 ma dc current vcc and gnd pins ............................... 300.0 ma dc characteristics t a = -40 c to 85 c, v cc = 2.7v to 6.0v (unless otherwise noted) symbol parameter condition min typ max units v il input low voltage except (xtal, reset ) -0.5 0.3 v cc (1) v v il1 input low voltage xtal -0.5 0.2 v cc (1) v reset v ih input high voltage except (xtal, reset ) 0.7 v cc (2) v cc + 0.5 v v ih1 input high voltage xtal 0.7 v cc (2) v cc + 0.5 v v ih2 input high volt age reset 0.85 v cc (2) v cc + 0.5 v v ol output low voltage (3) (ports b, c, d) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.6 0.5 v v oh output high voltage (4) (ports b, c, d) i oh = -3 ma, v cc = 5v i oh = -1.5 ma, v cc = 3v 4.3 2.2 v i il input leakage current i/o pin v cc = 6v, pin = low (absolute value) 8.0 a i ih input leakage current i/o pin v cc = 6v, pin = high (absolute value) 8.0 a rrst reset pull-up 100.0 500.0 k ? r i/o i/o pin pull-up resistor 35.0 120.0 k ? i cc power supply current active 4 mhz, v cc = 3v 5.0 ma idle 4 mhz, v cc = 3v 2.0 ma power-down, v cc = 3v wdt enabled (5) 20.0 a power-down, v cc = 3v wdt disabled (5) 10.0 a 99 at90s/ls4433 1042h?avr?04/03 notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low (logical ?0?). 2. ?min? means the lowest value where the pin is guaranteed to be read as high (logical ?1?). 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5.0v, 10 ma at v cc = 3.0v) under steady- state conditions (non-transient), the following must be observed: 1] the sum of all i ol , for all ports, should not exceed 300 ma. 2] the sum of all i ol , for ports c0 - c5, should not exceed 100 ma. 3] the sum of all i ol , for ports b0 - b5, d0 - d7 and xtal2, should not exceed 200 ma. if i ol exceeds the test condition, v ol may exceed the related specification. pi ns are not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (3 ma at v cc = 5.0v, 1.5 ma at v cc = 3.0v) under steady- state conditions (non-transient), the following must be observed: 1] the sum of all i oh , for all ports, should not exceed 300 ma. 2] the sum of all i oh , for ports c0 - c5, should not exceed 100 ma. 3] the sum of all i oh , for ports b0 - b5, d0 - d7 and xtal2, should not exceed 200 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 5. minimum v cc for power-down is 2.0v. v acio analog comparator input offset voltage v cc = 5.0v v in = v cc /2 40.0 mv i aclk analog comparator input leakage a v cc = 5.0v v in = v cc /2 -50.0 50.0 na t acpd analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750.0 500.0 ns dc characterist ics (continued) t a = -40 c to 85 c, v cc = 2.7v to 6.0v (unless otherwise noted) symbol parameter condition min typ max units 100 at90s/ls4433 1042h?avr?04/03 external clock drive waveforms figure 69. external clock table 39. external clock drive symbol parameter v cc = 2.7v to 6.0v v cc = 4.0v to 6.0v units min max min max 1/t clcl oscillator frequency 0.0 4.0 0.0 8.0 mhz t clcl clock period 250.0 125.0 ns t chcx high time 100.0 50.0 ns t clcx low time 100.0 50.0 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s vil1 vih1 101 at90s/ls4433 1042h?avr?04/03 typical characteristics the following charts show typical behavior. these figures are not tested during manu- facturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail- to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors, such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l v cc f, where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaran- teed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the dif- ferential current drawn by the watchdog timer. the difference between power-down mode with brown-out detector enabled and power-down mode with watchdog timer dis abled represents the differential current drawn by the brown-out detector. figure 70. active supply current vs. frequency 0 5 10 15 20 25 30 35 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 active supply current vs. frequency t a = 25?c v cc = 6v v cc = 5.5v v cc = 5v v cc = 4.5v v cc = 4v v cc = 3.6v v cc = 3.3v v cc = 3.0v v cc = 2.7v frequency (mhz) i cc (ma) 102 at90s/ls4433 1042h?avr?04/03 figure 71. active supply current vs. v cc figure 72. idle supply current vs. frequency 0 2 4 6 8 10 12 14 2 2.5 3 3.5 4 4.5 5 5.5 6 active supply current vs. v cc frequency = 4 mhz i cc (ma) v cc (v) t = 25 ? c a t = 85 ? c a 0 2 4 6 8 10 12 14 16 18 0 1 2 3 4 5 6 7 8 9 101112131415 v cc = 6v v cc = 5.5v v cc = 5v v cc = 4.5v v cc = 4v v cc = 3.6v v cc = 3.3v v cc = 3.0v v cc = 2.7v idle supply current vs. frequency t a = 25?c frequency (mhz) i cc (ma) 103 at90s/ls4433 1042h?avr?04/03 figure 73. idle supply current vs. v cc figure 74. power-down supply current vs. v cc t a = 25?c t a = 85?c idle supply current vs. v cc i cc (ma) v cc (v) frequency = 4 mhz 0 1 2 3 4 5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 0 5 10 15 20 25 2 2.5 3 3.5 4 4.5 5 5.5 6 t a = 85?c t a = 25?c power-down supply current vs. v cc i cc (a) v cc (v) watchdog timer disabled t a = 45?c t a = 70?c 104 at90s/ls4433 1042h?avr?04/03 figure 75. power-down supply current vs. v cc figure 76. power-down supply current vs. v cc 0 20 40 60 80 100 120 2 2.5 3 3.5 4 4.5 5 5.5 6 power-down supply current vs. v cc i cc (a) v cc (v) watchdog timer enabled t a = 85?c t a = 25?c 0 20 40 60 80 100 120 140 2 2.5 3 3.5 4 4.5 5 5.5 6 t a = 85?c t a = 25?c power-down supply current vs. v cc i cc (a) v cc (v) brown-out detector enabled 105 at90s/ls4433 1042h?avr?04/03 figure 77. analog comparator current vs. v cc analog comparator offset voltage is measured as absolute offset. figure 78. analog comparator offset voltage vs. common mode voltage analog comparator current vs. v cc i cc (ma) v cc (v) t a = 25?c t a = 85?c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2 2.5 3 3.5 4 4.5 5 5.5 6 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 analog comparator offset voltage vs. common mode voltage v cc = 5v common mode voltage (v) offset voltage (mv) t a = 85?c t a = 25?c 106 at90s/ls4433 1042h?avr?04/03 figure 79. analog comparator offset voltage vs. common mode voltage figure 80. analog comparator input leakage current 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 analog comparator offset voltage vs. common mode voltage v cc = 2.7v common mode voltage (v) offset voltage (mv) t a = 85?c t a = 25?c 60 50 40 30 20 10 0 -10 0 0.5 1.5 1 2 2.5 3.5 3 4 4.5 5 6 6.5 7 5.5 analog comparator input leakage current v cc = 6v t a = 25?c i aclk (na) v in (v) 107 at90s/ls4433 1042h?avr?04/03 figure 81. watchdog oscillator frequency vs. v cc sink and source capabilities of i/o po rts are measured on one pin at a time. figure 82. pull-up resistor current vs. input voltage t a = 85?c t a = 25?c watchdog oscillator frequency vs. v cc v cc (v) f rc (khz) 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 pull-up resistor current vs. input voltage v cc = 5v i op (a) v op (v) t a = 85?c t a = 25?c 108 at90s/ls4433 1042h?avr?04/03 figure 83. pull-up resistor current vs. input voltage figure 84. i/o pin sink current vs. output voltage 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 pull-up resistor current vs. input voltage i op (a) v op (v) v cc = 2.7v t a = 85?c t a = 25?c 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v cc = 5v i ol (ma) v ol (v) t a = 85?c t a = 25?c i/o pin sink current vs. output voltage 109 at90s/ls4433 1042h?avr?04/03 figure 85. i/o pin source current vs. output voltage figure 86. i/o pin sink current vs. output voltage 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i/o pin source current vs. output voltage v cc = 5v i oh (ma) v oh (v) t a = 85?c t a = 25?c 0 5 10 15 20 25 30 0 0.5 1 1.5 2 i ol (ma) v ol (v) t a = 85?c t a = 25?c i/o pin sink current vs. output voltage v cc = 2.7v 110 at90s/ls4433 1042h?avr?04/03 figure 87. i/o pin source current vs. output voltage figure 88. i/o pin input threshold voltage vs. v cc 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 i/o pin source current vs. output voltage i oh (ma) v oh (v) t a = 85?c t a = 25?c v cc = 2.7v 0 0.5 1 1.5 2 2.5 2.7 4.0 5.0 threshold voltage (v) v cc i/o pin input threshold voltage vs. v cc t a = 25?c 111 at90s/ls4433 1042h?avr?04/03 figure 89. i/o pin input hysteresis vs. v cc 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 2.7 4.0 5.0 input hysteresis (v) v cc i/o pin input hysteresis vs. v cc t a = 25?c 112 at90s/ls4433 1042h?avr?04/03 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f ($5f) sreg i t h s v n z c page 19 $3e ($5e) reserved ? ? ? ? ? ? ? ? page 20 $3d ($5d) sp sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 20 $3c ($5c) reserved $3b ($5b) gimsk int1 int0 ? ? ? ? ? ? page 27 $3a ($5a) gifr intf1 intf0 page 27 $39 ($59) timsk toie1 ocie1 ? ? ticie1 ? toie0 ? page 28 $38 ($58) tifr tov1 ocf1 ? ?icf1 ?tov0 ? page 29 $37 ($57) reserved $36 ($56) reserved $35 ($55) mcucr ? se sm isc11 isc10 isc01 isc00 page 30 $34 ($54) mcusr ? ? ? ? wdrf borf extrf porf page 26 $33 ($53) tccr0 ? ? ? ? ? cs02 cs01 cs00 page 34 $32 ($52) tcnt0 timer/counter0 (8 bits) page 35 $31 ($51) reserved $30 ($50) reserved $2f ($4f) tccr1a com11 com10 ? ? ? ? pwm11 pwm10 page 37 $2e ($4e) tccr1b icnc1 ices1 ? ? ctc1 cs12 cs11 cs10 page 38 $2d ($4d) tcnt1h timer/counter1 ? counter register high byte page 39 $2c ($4c) tcnt1l timer/counter1 ? counter register low byte page 39 $2b ($4b) ocr1h timer/counter1 ? output compare register high byte page 40 $2a ($4a) ocr1l timer/counter1 ? output compare register low byte page 40 $29 ($49) reserved $28 ($48) reserved $27 ($47) icr1h timer/counter1 ? input capture register high byte page 41 $26 ($46) icr1l timer/counter1 ? input capture register low byte page 41 $25 ($45) reserved $24 ($44) reserved $23 ($43) reserved $22 ($42) reserved $21 ($41) wdtcr ? ? ? wdtoe wde wdp2 wdp1 wdp0 page 43 $20 ($40) reserved $1f ($3f) reserved $1e ($3e) eear eeprom address register page 45 $1d ($3d) eedr eeprom data register page 45 $1c ($3c) eecr ? ? ? ? eerie eemwe eewe eere page 45 $1b ($3b) reserved $1a ($3a) reserved $19 ($39) reserved $18 ($38) portb ? ? portb5 portb4 portb3 portb2 portb1 portb0 page 72 $17 ($37) ddrb ? ? ddb5 ddb4 ddb3 ddb 2 ddb1 ddb0 page 72 $16 ($36) pinb ? ? pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 72 $15 ($35) portc ? ? portc5 portc4 portc3 portc2 portc1 portc0 page 78 $14 ($34) ddrc ? ? ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 78 $13 ($33) pinc ? ? pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 page 78 $12 ($32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 80 $11 ($31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 80 $10 ($30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 page 80 $0f ($2f) spdr spi data register page 52 $0e ($2e) spsr spif wcol ? ? ? ? ? ? page 52 $0d ($2d) spcr spie spe dord mstr cpol cpha spr1 spr0 page 51 $0c ($2c) udr uart i/o data register page 57 $0b ($2b) ucsra rxc txc udre fe or ? ? ? page 57 $0a ($2a) ucsrb rxcie txcie udrie rxen txen chr9 rxb8 txb8 page 58 $09 ($29) ubrr uart baud rate register page 61 $08 ($28) acsr acd ainbg aco aci acie acic acis1 acis0 page 62 $07 ($27) admux ? adcbg ? ? ? mux2 mux1 mux0 page 68 $06 ($26) adcsr aden adsc adfr ad if adie adps2 adps1 adps0 page 68 $05 ($25) adch ? ? ? ? ? ? adc9 adc8 page 69 $04 ($24) adcl adc7 adc6 adc5 ad c4 adc3 adc2 adc1 adc0 page 69 $03 ($23) ubrrhi uart baud rate register high page 61 $02 ($22) reserved $01 ($21) reserved $00 ($20) reserved 113 at90s/ls4433 1042h?avr?04/03 notes: 1. for compatibility with future devices, reserved bits shoul d be written to zero if accessed. reserved i/o memory address es should never be written. 2. some of the status flags are cleared by writing a logical ?1? to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers $00 to $1f only. 114 at90s/ls4433 1042h?avr?04/03 instruction set summary mnemonic operands description operation flags # clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl, k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl, k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff - rd z,c,n,v 1 neg rd two?s complement rd $00 - rd z,c,n,v,h 1 sbr rd, k set bit(s) in register rd rd v k z,n,v 1 cbr rd, k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd - 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd, rr compare rd - rr z,n,v,c,h 1 cpc rd, rr compare with carry rd - rr - c z,n,v,c,h 1 cpi rd, k compare register with immediate rd - k z,n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b) = 1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b) = 0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b) = 1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v = 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v = 1) then pc pc + k + 1 none 1/2 brhs k branch if half-carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half-carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t-flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t-flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 data transfer instructions mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, -x load indirect and pre-dec. x x - 1, rd (x) none 2 115 at90s/ls4433 1042h?avr?04/03 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, -y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z + 1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st -x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st -y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q, rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q, rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1none2 cbi p, b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c, rd(n+1) rd(n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd(n) rd(n+1), c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4), rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear ze ro flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half-carry flag in sreg h 1h1 clh clear half-carry flag in sreg h 0h1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued) mnemonic operands description operation flags # clocks 116 at90s/ls4433 1042h?avr?04/03 ordering information power supply speed (mhz) ordering code package operation range 2.7 - 6.0v 4 at90ls4433-4ac at90ls4433-4pc 32a 28p3 commercial (0 c to 70 c) at90ls4433-4ai at90ls4433-4pi 32a 28p3 industrial (-40 c to 85 c) 4.0 - 6.0v 8 at90s4433-8ac at90s4433-8pc 32a 28p3 commercial (0 c to 70 c) at90s4433-8ai at90s4433-8pi 32a 28p3 industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0 mm) plastic quad flat package (tqfp) 28p3 28-lead, 0.300" wide, plastic dual inline package (pdip) 117 at90s/ls4433 1042h?avr?04/03 packaging information 32a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ common dimensions (unit of measure = mm) symbol min nom max note 118 at90s/ls4433 1042h?avr?04/03 28p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28p3 , 28-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 28p3 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb b2 (4 places) common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.5724 a1 0.508 ? ? d 34.544 ? 34.798 note 1 e 7.620 ? 8.255 e1 7.112 ? 7.493 note 1 b 0.381 ? 0.533 b1 1.143 ? 1.397 b2 0.762 ? 1.143 l 3.175 ? 3.429 c 0.203 ? 0.356 eb ? ? 10.160 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010"). 119 at90s/ls4433 1042h?avr?04/03 errata for at90s/ls4433 rev. rev. c/d/e/f bod keeps the device in reset at low temperature fuses and programming mode incorrect channel change in free running mode bandgap reference stabilizing time brown-out detection level serial programming at voltages below 2.9v uart loses synchronization if rxd line is low when uart receive is disabled 7. bod keeps the device in reset at low temperature when the device operates at low temperature (below 0 c) and the bod is enabled, tha part may fail to start up. at low temperature the bod may never release the reset, and the part will not start the application. the problem will only occur during start-up and an already running application wil not go into reset even if the temperature goes below 0 c. note that this also affects the described workaround for errata no. 4. problem fix/workaround if the device operates at low temperature and a bod is required, an external bod circuit must be used. alternatively, atmega8 can be used instead of at90s/ls4433. 6. fuses and programming mode after programming the fuses in serial programming mode, it is not possible to pro- gram the flash or eeprom. if leaving programming mode, it is not possible to re- enter programming mode. problem fix/workaround power the part down and backup again after programming the fuses or leaving pro- gramming mode. 5. incorrect channel change in free running mode if the adc operates in free running mode and channels are changed by writing to admux, shortly after the adc interrupt fl ag (adif in adcsr) is set, the new set- ting in admux may affect the ongoing conversion. problem fix/workaround use single conversion mode when scanning channels, or avoid changing admux util at least 0.5 adc clock cycles after adif goes high. 4. bandgap reference stabilizing time the time for the internal vo ltage reference for the anal og comparator to stabilize is longer than specified. the stabilizing period starts after the bandgap reference has been selected, and can go on for as much as 10 seconds. problem fix/workaround the bandgap reference will be stable immedi ately if the internal brown-out detector is enabled. 120 at90s/ls4433 1042h?avr?04/03 3. brown-out detection level the brown-out detection level can increase when there is heavy i/o-activity on the device. the increase can be significant when some of the i/o pins are driving heavy loads. problem fix/workaround select a v cc well above the brown-out detection level. avoid loading i/o ports with high capacitive or resistive loads. 2. serial programming at voltages below 2.9v at voltages below 2.9v, serial programming might fail. problem fix/workaround keep v cc at 2.9v or higher during in-system programming. 1. uart loses synchronization if rxd line is low when uart receive is disabled the uart will detect a uart start bit and start reception even if the uart is not enabled. if this occurs, t he first byte after reenablin g the uart will be corrupted. problem fix/workaround make sure that the rx line is high at start-up and when the uart is disabled. an external rs-232 level converter keeps the line high during start-up. 121 at90s/ls4433 1042h?avr?04/03 data sheet change log for at90s/ls4433 this section containes a log on the changes made to the data sheet for at90s/ls4433. all refereces to pages in change log, are referred to this document. changes from rev. 1042e-09/01 to ref. 1042f-03/02 1 updated minimum aref voltage on page 5 and page 64. 2 corrected vbot max for bodl evel = 1 in table 4 on page 22. 3 updated corporate template. changes from rev. 1042f-03/02 to ref. 1042g-09/02 1 added wathermark ?not recommended for new designs. use atmega8?. 2 added errata sheet to the data sheet. changes from rev. 1042g-09/02 to ref. 1042h-04/03 1 updated the ?errata for at90s/ls4433 rev. rev. c/d/e/f? on page 119. 2 updated ?packaging information? on page 117. 122 at90s/ls4433 1042h?avr?04/03 i at90s/ls4433 1042h?avr?04/03 table of contents features............... ................. .............. .............. .............. .............. ......... 1 pin configurations............... .............. .............. .............. .............. ......... 2 description .......... ................. .............. .............. .............. .............. ......... 3 block diagram ...................................................................................................... 4 pin descriptions.................................................................................................... 5 clock options ....................................................................................................... 6 architectural overview........ .............. .............. .............. .............. ......... 7 general purpose register file ........................................................................... 10 alu ? arithmetic logic unit................................................................................ 11 in-system programmable flash program memory ............................................ 11 sram data memory........................................................................................... 11 program and data addressing modes................................................................ 12 eeprom data memory............. ................ ................ ................ ................ ......... 16 memory access times and instruction execution timing .................................. 16 i/o memory ......................................................................................................... 17 reset and interrupt handling.............................................................................. 20 sleep modes....................................................................................................... 31 timer/counters .......... ................. ................ ................. .............. ......... 33 timer/counter prescaler..................................................................................... 33 8-bit timer/counter0........................................................................................... 33 16-bit timer/counter1............ ................ ................. ................ ............ 35 watchdog timer............ ................ ................. .............. .............. ......... 43 eeprom read/write access..... ................ ................. .............. ......... 45 prevent eeprom corruption ............................................................................. 47 serial peripheral interface ? spi................... .............. .............. ......... 48 ss pin functionality............................................................................................ 49 data modes ........................................................................................................ 50 uart............. ................. ................ ................. .............. .............. ......... 53 data transmission.............................................................................................. 53 data reception ................................................................................................... 54 uart control ..................................................................................................... 57 analog comparator ............... ................ ................. ................ ............ 62 ii at90s/ls4433 1042h?avr?04/03 analog-to-digital converter... ............... ................. ................ ............ 64 features.............................................................................................................. 64 operation ............................................................................................................ 65 prescaling ........................................................................................................... 65 adc noise canceler function............................................................................ 67 scanning multiple channels ............................................................................... 70 adc noise canceling techniques ..................................................................... 70 adc characteristics t a = -40 c to 85 c ............................................................ 71 i/o ports............. ................ .............. ............... .............. .............. ......... 72 port b.................................................................................................................. 72 port c.................................................................................................................. 77 port d.................................................................................................................. 80 memory programming........... ................ ................. ................ ............ 85 program and data memory lock bits................................................................. 85 fuse bits............................................................................................................. 85 signature bytes .................................................................................................. 85 programming the flash and eeprom............ ................. ................ ............. ..... 86 parallel programming ......................................................................................... 86 parallel programming characteristics ................................................................ 92 serial downloading............................................................................................. 93 serial programming characteristics ................................................................... 97 electrical characteristics...... ................ ................. ................ ............ 98 absolute maximum ratings*............................................................................... 98 dc characteristics.............................................................................................. 98 external clock drive wavef orms ............ ................ .............. .......... 100 typical characteristics ......... ................ ................. ................ .......... 101 register summary ..... ................. ................ .............. .............. .......... 112 instruction set summary ...... ................ ................. ................ .......... 114 ordering information........... ................ ................. ................ ............ 116 packaging information .......... ................ ................. ................ .......... 117 32a ................................................................................................................... 117 28p3 ................................................................................................................. 118 errata for at90s/ls4433 rev. rev. c/d/e/f........... .............. .......... 119 iii at90s/ls4433 1042h?avr?04/03 data sheet change log fo r at90s/ls4433............ .............. .......... 121 changes from rev. 1042e-09/01 to ref. 1042f-03/02 .................................... 121 changes from rev. 1042f-03/02 to ref. 1042g-09/02.................................... 121 changes from rev. 1042g-09/02 to ref. 1042h-04/03 ................................... 121 table of contents ................ .............. .............. .............. .............. .......... i printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products , other than those expressly c ontained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devi ces or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein . no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, ex pressly or by implication. at mel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 1042h?avr?04/03 0m at m e l ? and avr ? are the registered trademarks of atmel. other terms and product names may be the trademarks of others. |
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